Searched refs:x9 (Results 1 – 25 of 144) sorted by relevance
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85 mrs x9, mdscr_el193 stp x8, x9, [x0, #48]114 ldp x9, x10, [x0, #48]134 msr vbar_el1, x9237 end_pudp .req x9464 tcr_clear_errata_bits tcr, x9, x5467 ldr_l x9, vabits_actual468 sub x9, xzr, x9469 add x9, x9, #64470 tcr_set_t1sz tcr, x9[all …]
69 reg = <0x9>;85 reg = <0x9>;101 reg = <0x9>;117 reg = <0x9>;133 reg = <0x9>;149 reg = <0x9>;165 reg = <0x9>;181 reg = <0x9>;
92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;246 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0247 0x81000000 0 0 0x81000000 0x9 0 1 0>;
31 ldp x8, x9, [x1, #48]52 stnp x8, x9, [x0, #48 - 256]53 ldp x8, x9, [x1, #48]71 stnp x8, x9, [x0, #48 - 256]
48 stp x8, x9, [sp, #8 * 8]63 ldp x8, x9, [sp, #8 * 8]
46 ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]47 cmp x9, #ARM_SMCCC_QUIRK_QCOM_A688 ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]104 stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
45 stp x8, x9, [sp, #S_X8]65 stp x9, x10, [sp, #S_LR]71 stp x29, x9, [sp, #PT_REGS_SIZE]91 mov x1, x9 // parent_ip (callsite's LR)120 ldr x9, [sp, #S_PC]125 ret x9
80 adr_l x9, mpidr_hash81 ldr x10, [x9, #MPIDR_HASH_MASK]86 ldp w3, w4, [x9, #MPIDR_HASH_SHIFTS]87 ldp w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)]
763 add x9, x9, x11 // __va(.rela)764 add x10, x9, x10 // __va(.rela) + sizeof(.rela)766 0: cmp x9, x10768 ldp x12, x13, [x9], #24769 ldr x14, [x9, #-8]816 add x9, x9, x11 // __va(.relr)817 add x10, x9, x10 // __va(.relr) + sizeof(.relr)823 2: cmp x9, x10825 ldr x11, [x9], #8
200 stp x8, x9, [sp, #16 * 4]405 ldp x8, x9, [sp, #16 * 4]724 mov x9, sp730 stp x29, x9, [x8], #16738 ldp x29, x9, [x8], #16740 mov sp, x9742 ptrauth_keys_install_kernel x1, x8, x9, x10894 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
255 add x9, x8, #32257 sub x9, x9, x4259 ld1 {v4.16b}, [x9]284 add x9, x8, #32286 sub x9, x9, x4288 ld1 {v4.16b}, [x9]383 sub x9, x12, #MAX_STRIDE - 3387 rev x9, x9391 mov v3.d[1], x9567 add x9, x8, #32[all …]
495 lsl x9, rounds, #7496 add bskey, bskey, x9896 99: mov x9, #1897 lsl x9, x9, x23900 csel x9, x9, xzr, le902 tbnz x9, #1, 0f904 tbnz x9, #2, 0f906 tbnz x9, #3, 0f908 tbnz x9, #4, 0f910 tbnz x9, #5, 0f[all …]
235 { const u32 x9 = in1[2]; in fe_add_impl() local250 out[2] = (x9 + x27); in fe_add_impl()278 { const u32 x9 = in1[2]; in fe_sub_impl() local293 out[2] = ((0x7fffffe + x9) - x27); in fe_sub_impl()321 { const u32 x9 = in1[2]; in fe_mul_impl() local336 { u64 x42 = ((((u64)(0x2 * x25) * x7) + ((u64)x23 * x9)) + ((u64)x27 * x5)); in fe_mul_impl()337 { u64 x43 = (((((u64)x25 * x9) + ((u64)x27 * x7)) + ((u64)x23 * x11)) + ((u64)x29 * x5)); in fe_mul_impl()338 …{ u64 x44 = (((((u64)x27 * x9) + (0x2 * (((u64)x25 * x11) + ((u64)x29 * x7)))) + ((u64)x23 * x13))… in fe_mul_impl()339 …{ u64 x45 = (((((((u64)x27 * x11) + ((u64)x29 * x9)) + ((u64)x25 * x13)) + ((u64)x31 * x7)) + ((u6… in fe_mul_impl()340 … + ((u64)x25 * x15)) + ((u64)x33 * x7))) + ((u64)x27 * x13)) + ((u64)x31 * x9)) + ((u64)x23 * x17)… in fe_mul_impl()[all …]
220 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2224 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2228 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2232 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2236 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2240 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2244 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2248 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
29 stp x8, x9, [x0, #CPU_XREG_OFFSET(8)]51 ldp x8, x9, [x29, #CPU_XREG_OFFSET(8)]221 ldp x8, x9, [x18, #CPU_XREG_OFFSET(8)]233 stp x8, x9, [x18, #CPU_XREG_OFFSET(8)]
53 reg = <0x9>; /* SPI */67 reg = <0x9>; /* SPI */
9 stp x8, x9, [sp, #16 * 4]52 ldp x8, x9, [sp, #16 * 4]
17 stp x8, x9, [sp, #S_X8]51 ldp x8, x9, [sp, #S_X8]
78 #define O9(x1, x2, x3, x4, x5, x6, x7, x8, x9) \ argument80 O(x1), O(x2), O(x3), O(x4), O(x5), O(x6), O(x7), O(x8), O(x9), \117 #define RV9(x1, x2, x3, x4, x5, x6, x7, x8, x9) \ argument120 [x9] = V(x9),
131 0x8000 0x0 0x0 0x1 &mpic 0x9 0x1138 0x8800 0x0 0x0 0x2 &mpic 0x9 0x1148 0xa000 0x0 0x0 0x1 &mpic 0x9 0x1
21 REG_S x9, PT_S1(sp)53 REG_L x9, PT_S1(sp)
46 <0x9 &iommu0 0x9 0xfff7>;
73 ldp x8, x9, [x29, #CPU_XREG_OFFSET(8)]128 stp x8, x9, [x1, #CPU_XREG_OFFSET(8)]
109 byte 0: 1 0 0 0 1 x9 x8 x7123 byte 2: 0 x10 x9 x8 x7 ? fin ges141 byte 2: 0 x10 x9 x8 x7 0 fin ges164 byte 1: 0 x10 x9 x8 x7 x6 x5 x4183 byte 4: 0 x14 x13 x12 x11 x10 x9 y0208 byte 1: 0 x10 x9 x8 x7 x6 x5 x4223 byte 3: 0 x9 x8 y9 y8 y7 y6 y5259 byte 4: y10 y9 y8 y7 x10 x9 x8 x7268 byte 4: 0 x9 x8 x7 x6 x5 x4 x3
316 # x9 += x13, x5 = rotl32(x5 ^ x9, 12)370 # x9 += x13, x5 = rotl32(x5 ^ x9, 7)438 # x9 += x14, x4 = rotl32(x4 ^ x9, 12)492 # x9 += x14, x4 = rotl32(x4 ^ x9, 7)538 # x9[0-3] += s2[1]
