Searched refs:wrpll (Results 1 – 5 of 5) sorted by relevance
3 obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
193 u32 wrpll; member
585 intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()648 hw_state->wrpll = val; in hsw_ddi_wrpll_get_hw_state()907 crtc_state->dpll_hw_state.wrpll = val; in hsw_ddi_wrpll_get_dpll()926 u32 wrpll = pll_state->wrpll; in hsw_ddi_wrpll_get_freq() local928 switch (wrpll & WRPLL_REF_MASK) { in hsw_ddi_wrpll_get_freq()948 MISSING_CASE(wrpll); in hsw_ddi_wrpll_get_freq()952 r = wrpll & WRPLL_DIVIDER_REF_MASK; in hsw_ddi_wrpll_get_freq()953 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; in hsw_ddi_wrpll_get_freq()954 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; in hsw_ddi_wrpll_get_freq()1102 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()[all …]
1111 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); in i915_shared_dplls_info()
8740 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); in intel_pipe_config_compare()
