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Searched refs:wptr_offs (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c75 unsigned wptr_offs, rptr_offs; in amdgpu_ih_ring_init() local
77 r = amdgpu_device_wb_get(adev, &wptr_offs); in amdgpu_ih_ring_init()
83 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
93 amdgpu_device_wb_free(adev, wptr_offs); in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
98 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; in amdgpu_ih_ring_init()
Damdgpu_ring.c206 r = amdgpu_device_wb_get(adev, &ring->wptr_offs); in amdgpu_ring_init()
293 amdgpu_device_wb_free(ring->adev, ring->wptr_offs); in amdgpu_ring_fini()
Djpeg_v3_0.c425 return adev->wb.wb[ring->wptr_offs]; in jpeg_v3_0_dec_ring_get_wptr()
442 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v3_0_dec_ring_set_wptr()
Djpeg_v2_5.c402 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_5_dec_ring_get_wptr()
419 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_5_dec_ring_set_wptr()
Dvcn_v2_0.c1336 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_dec_ring_get_wptr()
1357 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_dec_ring_set_wptr()
1565 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1570 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1589 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
1596 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
Dsdma_v5_2.c263 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v5_2_ring_get_wptr()
292 ring->wptr_offs, in sdma_v5_2_ring_set_wptr()
296 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
297 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
633 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_2_gfx_resume()
Dsdma_v4_0.c743 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_ring_get_wptr()
769 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_ring_set_wptr()
775 ring->wptr_offs, in sdma_v4_0_ring_set_wptr()
812 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_0_page_ring_get_wptr()
834 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v4_0_page_ring_set_wptr()
1226 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_gfx_resume()
1317 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_page_resume()
Djpeg_v2_0.c430 return adev->wb.wb[ring->wptr_offs]; in jpeg_v2_0_dec_ring_get_wptr()
447 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
Dmes_v10_1.c49 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], in mes_v10_1_ring_set_wptr()
68 &ring->adev->wb.wb[ring->wptr_offs]); in mes_v10_1_ring_get_wptr()
682 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in mes_v10_1_mqd_init()
Dsdma_v3_0.c370 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; in sdma_v3_0_ring_get_wptr()
390 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
395 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; in sdma_v3_0_ring_set_wptr()
718 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v3_0_gfx_resume()
Dvcn_v2_5.c1496 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_dec_ring_get_wptr()
1513 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_dec_ring_set_wptr()
1610 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1615 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_5_enc_ring_get_wptr()
1634 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
1641 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_5_enc_ring_set_wptr()
Dsdma_v5_0.c376 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v5_0_ring_get_wptr()
405 ring->wptr_offs, in sdma_v5_0_ring_set_wptr()
409 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
410 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
752 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v5_0_gfx_resume()
Dvce_v4_0.c86 return adev->wb.wb[ring->wptr_offs]; in vce_v4_0_ring_get_wptr()
109 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
180 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; in vce_v4_0_mmsch_start()
Dvcn_v3_0.c1718 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_dec_ring_get_wptr()
1744 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_dec_ring_set_wptr()
2030 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_enc_ring_get_wptr()
2035 return adev->wb.wb[ring->wptr_offs]; in vcn_v3_0_enc_ring_get_wptr()
2054 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_enc_ring_set_wptr()
2061 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v3_0_enc_ring_set_wptr()
Damdgpu_ring.h235 unsigned wptr_offs; member
Duvd_v7_0.c120 return adev->wb.wb[ring->wptr_offs]; in uvd_v7_0_enc_ring_get_wptr()
155 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
763 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; in uvd_v7_0_mmsch_start()
Dgfx_v9_0.c849 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_kiq_map_queues()
3345 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_cp_gfx_resume()
3563 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_0_mqd_init()
3845 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); in gfx_v9_0_kcq_init_queue()
5283 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_gfx()
5298 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_gfx()
5472 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v9_0_ring_get_wptr_compute()
5484 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v9_0_ring_set_wptr_compute()
Dgfx_v8_0.c4313 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_cp_gfx_resume()
4396 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_kiq_kcq_enable()
4526 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_mqd_init()
6059 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_gfx()
6070 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_gfx()
6270 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_compute()
6278 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v8_0_ring_set_wptr_compute()
Dgfx_v10_0.c3628 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx10_kiq_map_queues()
6404 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
6441 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_cp_gfx_resume()
6665 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_gfx_mqd_init()
6779 adev->wb.wb[ring->wptr_offs] = 0; in gfx_v10_0_gfx_init_queue()
6959 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v10_0_compute_mqd_init()
7179 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); in gfx_v10_0_kcq_init_queue()
8506 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_gfx()
8521 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); in gfx_v10_0_ring_set_wptr_gfx()
8540 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); in gfx_v10_0_ring_get_wptr_compute()
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Dgfx_v7_0.c2680 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()
2688 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in gfx_v7_0_ring_set_wptr_compute()
2984 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_mqd_init()
/Linux-v5.15/drivers/gpu/drm/radeon/
Dcik.c4164 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()
4180 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; in cik_compute_set_wptr()
8413 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET; in cik_startup()
8425 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET; in cik_startup()
Dradeon.h860 unsigned wptr_offs; member