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Searched refs:wave (Results 1 – 19 of 19) sorted by relevance

/Linux-v5.15/sound/pci/emu10k1/
Demu10k1.c91 struct snd_seq_device *wave = NULL; in snd_card_emu10k1_probe() local
165 sizeof(struct snd_emu10k1_synth_arg), &wave) < 0 || in snd_card_emu10k1_probe()
166 wave == NULL) { in snd_card_emu10k1_probe()
171 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_card_emu10k1_probe()
172 strcpy(wave->name, "Emu-10k1 Synth"); in snd_card_emu10k1_probe()
/Linux-v5.15/sound/pci/
Dad1889.c90 struct ad1889_register_state wave; member
190 chip->wave.reg = reg; in ad1889_channel_reset()
358 chip->wave.size = size; in snd_ad1889_playback_prepare()
359 chip->wave.reg = reg; in snd_ad1889_playback_prepare()
360 chip->wave.addr = rt->dma_addr; in snd_ad1889_playback_prepare()
362 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); in snd_ad1889_playback_prepare()
368 ad1889_load_wave_buffer_address(chip, chip->wave.addr); in snd_ad1889_playback_prepare()
379 chip->wave.addr, count, size, reg, rt->rate); in snd_ad1889_playback_prepare()
460 chip->wave.reg = wsmc; in snd_ad1889_playback_trigger()
516 if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN))) in snd_ad1889_playback_pointer()
[all …]
/Linux-v5.15/sound/pci/au88x0/
Dau88x0.c267 sizeof(snd_vortex_synth_arg_t), &wave) < 0 in snd_vortex_probe()
268 || wave == NULL) { in snd_vortex_probe()
273 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_vortex_probe()
274 strcpy(wave->name, "Aureal Synth"); in snd_vortex_probe()
/Linux-v5.15/Documentation/devicetree/bindings/rtc/
Dmaxim,ds3231.txt14 - 0: square-wave output on the SQW pin
15 - 1: square-wave output on the 32kHz pin
Drtc-m41t80.txt25 - clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
439 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
468 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_wait_for_waves_assigned()
469 if (((1 << wave) & mask) && in gfx_v9_4_2_wait_for_waves_assigned()
1821 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1824 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
1835 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1847 wave = i % cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1849 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_2_log_cu_timeout_status()
[all …]
Dgfx_v6_0.c2983 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2986 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2994 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2998 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
3008 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v6_0_read_wave_data() argument
3012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
3013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
3014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
3015 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
3016 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
[all …]
Damdgpu_gfx.h227 uint32_t wave, uint32_t *dst, int *no_fields);
229 uint32_t wave, uint32_t thread, uint32_t start,
232 uint32_t wave, uint32_t start, uint32_t size,
Dgfx_v7_0.c4154 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4157 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4165 uint32_t wave, uint32_t thread, in wave_read_regs() argument
4169 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4179 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v7_0_read_wave_data() argument
4183 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4184 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4185 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4186 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4187 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
[all …]
Damdgpu_debugfs.c830 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
840 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
861 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
922 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
932 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; in amdgpu_debugfs_gpr_read()
955 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
958 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
Dgfx_v8_0.c5235 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5238 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
5246 uint32_t wave, uint32_t thread, in wave_read_regs() argument
5250 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
5260 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v8_0_read_wave_data() argument
5264 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5265 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5266 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5267 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5268 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
[all …]
Dgfx_v9_0.c2050 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2053 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2061 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2065 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
2075 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v9_0_read_wave_data() argument
2079 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
2080 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
2081 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
2082 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
2083 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
[all …]
Dgfx_v10_0.c4579 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
4582 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
4587 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
4592 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
4600 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint… in gfx_v10_0_read_wave_data() argument
4609 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v10_0_read_wave_data()
4610 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v10_0_read_wave_data()
4611 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v10_0_read_wave_data()
4612 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v10_0_read_wave_data()
4613 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v10_0_read_wave_data()
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt18 - ti,clkmode-square-wave: Indicates that the the board is supplying a square
19 wave input on the OSCIN pin instead of using a crystal oscillator.
61 ti,clkmode-square-wave;
/Linux-v5.15/drivers/gpu/ipu-v3/
Dipu-dc.c120 int map, int wave, int glue, int sync, int stop) in dc_write_tmpl() argument
129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl()
132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-dfll.txt56 - nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
/Linux-v5.15/Documentation/virt/kvm/
Dtimekeeping.rst103 This generates a high / low square wave. The count
112 which generates sine-like tones by low-pass filtering the square wave output.
253 bit 3 = Square wave interrupt enable
/Linux-v5.15/Documentation/driver-api/media/drivers/
Dvidtv.rst34 Elementary Stream, which in turn contains a SMPTE 302m encoded sine-wave.
/Linux-v5.15/drivers/media/rc/
DKconfig374 wave and pulses.