| /Linux-v5.15/drivers/media/platform/mtk-vpu/ |
| D | mtk_vpu.c | 227 static inline void vpu_cfg_writel(struct mtk_vpu *vpu, u32 val, u32 offset) in vpu_cfg_writel() argument
229 writel(val, vpu->reg.cfg + offset); in vpu_cfg_writel()
232 static inline u32 vpu_cfg_readl(struct mtk_vpu *vpu, u32 offset) in vpu_cfg_readl() argument
234 return readl(vpu->reg.cfg + offset); in vpu_cfg_readl()
237 static inline bool vpu_running(struct mtk_vpu *vpu) in vpu_running() argument
239 return vpu_cfg_readl(vpu, VPU_RESET) & BIT(0); in vpu_running()
242 static void vpu_clock_disable(struct mtk_vpu *vpu) in vpu_clock_disable() argument
245 mutex_lock(&vpu->vpu_mutex); in vpu_clock_disable()
246 if (!--vpu->wdt_refcnt) in vpu_clock_disable()
247 vpu_cfg_writel(vpu, in vpu_clock_disable()
[all …]
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| /Linux-v5.15/drivers/media/platform/mtk-vcodec/ |
| D | vdec_vpu_if.c | 15 struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) in handle_init_ack_msg() local
18 mtk_vcodec_debug(vpu, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr); in handle_init_ack_msg()
22 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_init_ack_msg()
24 vpu->inst_addr = msg->vpu_inst_addr; in handle_init_ack_msg()
26 mtk_vcodec_debug(vpu, "- vpu_inst_addr = 0x%x", vpu->inst_addr); in handle_init_ack_msg()
42 struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) in vpu_dec_ipi_handler() local
45 mtk_vcodec_debug(vpu, "+ id=%X", msg->msg_id); in vpu_dec_ipi_handler()
60 mtk_vcodec_err(vpu, "invalid msg=%X", msg->msg_id); in vpu_dec_ipi_handler()
65 mtk_vcodec_debug(vpu, "- id=%X", msg->msg_id); in vpu_dec_ipi_handler()
66 vpu->failure = msg->status; in vpu_dec_ipi_handler()
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| D | venc_vpu_if.c | 12 static void handle_enc_init_msg(struct venc_vpu_inst *vpu, const void *data) in handle_enc_init_msg() argument
16 vpu->inst_addr = msg->vpu_inst_addr; in handle_enc_init_msg()
17 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_enc_init_msg()
21 if (vpu->ctx->dev->venc_pdata->chip == MTK_MT8173) in handle_enc_init_msg()
25 mtk_vcodec_debug(vpu, "firmware version: 0x%x\n", in handle_enc_init_msg()
31 mtk_vcodec_err(vpu, "unhandled firmware version 0x%x\n", in handle_enc_init_msg()
33 vpu->failure = 1; in handle_enc_init_msg()
38 static void handle_enc_encode_msg(struct venc_vpu_inst *vpu, const void *data) in handle_enc_encode_msg() argument
42 vpu->state = msg->state; in handle_enc_encode_msg()
43 vpu->bs_size = msg->bs_size; in handle_enc_encode_msg()
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| D | vdec_vpu_if.h | 43 int vpu_dec_init(struct vdec_vpu_inst *vpu);
53 int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t *data, unsigned int len);
63 int vpu_dec_end(struct vdec_vpu_inst *vpu);
70 int vpu_dec_deinit(struct vdec_vpu_inst *vpu);
78 int vpu_dec_reset(struct vdec_vpu_inst *vpu);
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| D | venc_vpu_if.h | 41 int vpu_enc_init(struct venc_vpu_inst *vpu);
42 int vpu_enc_set_param(struct venc_vpu_inst *vpu,
45 int vpu_enc_encode(struct venc_vpu_inst *vpu, unsigned int bs_mode,
50 int vpu_enc_deinit(struct venc_vpu_inst *vpu);
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| /Linux-v5.15/drivers/staging/media/hantro/ |
| D | hantro_g2_hevc_dec.c | 18 static inline void hantro_write_addr(struct hantro_dev *vpu, in hantro_write_addr() argument
22 vdpu_write(vpu, addr & 0xffffffff, offset); in hantro_write_addr()
27 struct hantro_dev *vpu = ctx->dev; in prepare_tile_info_buffer() local
42 hantro_reg_write(vpu, &g2_tile_e, tiles_enabled); in prepare_tile_info_buffer()
60 hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows); in prepare_tile_info_buffer()
61 hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols); in prepare_tile_info_buffer()
108 hantro_reg_write(vpu, &g2_num_tile_rows, 1); in prepare_tile_info_buffer()
109 hantro_reg_write(vpu, &g2_num_tile_cols, 1); in prepare_tile_info_buffer()
126 struct hantro_dev *vpu = ctx->dev; in set_params() local
132 hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8); in set_params()
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| D | hantro_drv.c | 59 static void hantro_job_finish_no_pm(struct hantro_dev *vpu, in hantro_job_finish_no_pm() argument
80 static void hantro_job_finish(struct hantro_dev *vpu, in hantro_job_finish() argument
84 pm_runtime_mark_last_busy(vpu->dev); in hantro_job_finish()
85 pm_runtime_put_autosuspend(vpu->dev); in hantro_job_finish()
87 clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); in hantro_job_finish()
89 hantro_job_finish_no_pm(vpu, ctx, result); in hantro_job_finish()
92 void hantro_irq_done(struct hantro_dev *vpu, in hantro_irq_done() argument
96 v4l2_m2m_get_curr_priv(vpu->m2m_dev); in hantro_irq_done()
103 if (cancel_delayed_work(&vpu->watchdog_work)) { in hantro_irq_done()
106 hantro_job_finish(vpu, ctx, result); in hantro_irq_done()
[all …]
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| D | imx8m_vpu_hw.c | 28 static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) in imx8m_soft_reset() argument
33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
35 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
40 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
42 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
45 static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) in imx8m_clk_enable() argument
49 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
51 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
54 static int imx8mq_runtime_resume(struct hantro_dev *vpu) in imx8mq_runtime_resume() argument
58 ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks); in imx8mq_runtime_resume()
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| D | hantro_postproc.c | 15 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ argument
17 hantro_reg_write(vpu, \
18 &(vpu)->variant->postproc_regs->reg_name, \
22 #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ argument
24 hantro_reg_write_s(vpu, \
25 &(vpu)->variant->postproc_regs->reg_name, \
56 struct hantro_dev *vpu = ctx->dev; in hantro_needs_postproc() local
61 if (!vpu->variant->postproc_fmts) in hantro_needs_postproc()
69 struct hantro_dev *vpu = ctx->dev; in hantro_postproc_enable() local
74 if (!vpu->variant->postproc_regs) in hantro_postproc_enable()
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| D | rockchip_vpu2_hw_jpeg_enc.c | 35 static void rockchip_vpu2_set_src_img_ctrl(struct hantro_dev *vpu, in rockchip_vpu2_set_src_img_ctrl() argument
46 vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); in rockchip_vpu2_set_src_img_ctrl()
56 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); in rockchip_vpu2_set_src_img_ctrl()
59 vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); in rockchip_vpu2_set_src_img_ctrl()
62 static void rockchip_vpu2_jpeg_enc_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_jpeg_enc_set_buffers() argument
71 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma, in rockchip_vpu2_jpeg_enc_set_buffers()
73 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size, in rockchip_vpu2_jpeg_enc_set_buffers()
78 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
82 vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0); in rockchip_vpu2_jpeg_enc_set_buffers()
83 vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1); in rockchip_vpu2_jpeg_enc_set_buffers()
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| D | hantro_h1_jpeg_enc.c | 18 static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu, in hantro_h1_set_src_img_ctrl() argument
28 vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); in hantro_h1_set_src_img_ctrl()
31 static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu, in hantro_h1_jpeg_enc_set_buffers() argument
40 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma, in hantro_h1_jpeg_enc_set_buffers()
42 vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size, in hantro_h1_jpeg_enc_set_buffers()
48 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
52 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
53 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
58 vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0); in hantro_h1_jpeg_enc_set_buffers()
59 vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1); in hantro_h1_jpeg_enc_set_buffers()
[all …]
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| D | rockchip_vpu2_hw_vp8_dec.c | 280 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
285 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
291 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
295 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
302 vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); in cfg_lf()
306 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
308 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
319 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
323 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
329 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
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| D | hantro_g1_vp8_dec.c | 139 struct hantro_dev *vpu = ctx->dev; in cfg_lf() local
144 hantro_reg_write(vpu, &vp8_dec_lf_level[0], lf->level); in cfg_lf()
150 hantro_reg_write(vpu, &vp8_dec_lf_level[i], lf_level); in cfg_lf()
154 hantro_reg_write(vpu, &vp8_dec_lf_level[i], in cfg_lf()
161 vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); in cfg_lf()
165 hantro_reg_write(vpu, &vp8_dec_mb_adj[i], in cfg_lf()
167 hantro_reg_write(vpu, &vp8_dec_ref_adj[i], in cfg_lf()
181 struct hantro_dev *vpu = ctx->dev; in cfg_qp() local
185 hantro_reg_write(vpu, &vp8_dec_quant[0], q->y_ac_qi); in cfg_qp()
191 hantro_reg_write(vpu, &vp8_dec_quant[i], quant); in cfg_qp()
[all …]
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| D | rockchip_vpu_hw.c | 208 struct hantro_dev *vpu = dev_id; in rockchip_vpu1_vepu_irq() local
212 status = vepu_read(vpu, H1_REG_INTERRUPT); in rockchip_vpu1_vepu_irq()
216 vepu_write(vpu, 0, H1_REG_INTERRUPT); in rockchip_vpu1_vepu_irq()
217 vepu_write(vpu, 0, H1_REG_AXI_CTRL); in rockchip_vpu1_vepu_irq()
219 hantro_irq_done(vpu, state); in rockchip_vpu1_vepu_irq()
226 struct hantro_dev *vpu = dev_id; in rockchip_vpu2_vdpu_irq() local
230 status = vdpu_read(vpu, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
234 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT); in rockchip_vpu2_vdpu_irq()
235 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL); in rockchip_vpu2_vdpu_irq()
237 hantro_irq_done(vpu, state); in rockchip_vpu2_vdpu_irq()
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| D | hantro_g1_h264_dec.c | 28 struct hantro_dev *vpu = ctx->dev; in set_params() local
49 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); in set_params()
55 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); in set_params()
65 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); in set_params()
71 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); in set_params()
85 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); in set_params()
100 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); in set_params()
107 vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); in set_params()
110 vdpu_write_relaxed(vpu, 0, G1_REG_ERR_CONC); in set_params()
113 vdpu_write_relaxed(vpu, in set_params()
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| D | rockchip_vpu2_hw_mpeg2_dec.c | 83 rockchip_vpu2_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_quantisation() argument
90 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, VDPU_REG_QTABLE_BASE); in rockchip_vpu2_mpeg2_dec_set_quantisation()
94 rockchip_vpu2_mpeg2_dec_set_buffers(struct hantro_dev *vpu, in rockchip_vpu2_mpeg2_dec_set_buffers() argument
114 vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
122 vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
140 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
142 vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE); in rockchip_vpu2_mpeg2_dec_set_buffers()
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| D | hantro_g1.c | 16 struct hantro_dev *vpu = dev_id; in hantro_g1_irq() local
20 status = vdpu_read(vpu, G1_REG_INTERRUPT); in hantro_g1_irq()
24 vdpu_write(vpu, 0, G1_REG_INTERRUPT); in hantro_g1_irq()
25 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_irq()
27 hantro_irq_done(vpu, state); in hantro_g1_irq()
34 struct hantro_dev *vpu = ctx->dev; in hantro_g1_reset() local
36 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); in hantro_g1_reset()
37 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); in hantro_g1_reset()
38 vdpu_write(vpu, 1, G1_REG_SOFT_RESET); in hantro_g1_reset()
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| D | hantro.h | 85 int (*init)(struct hantro_dev *vpu);
86 int (*runtime_resume)(struct hantro_dev *vpu);
335 static inline void vepu_write_relaxed(struct hantro_dev *vpu, in vepu_write_relaxed() argument
339 writel_relaxed(val, vpu->enc_base + reg); in vepu_write_relaxed()
342 static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg) in vepu_write() argument
345 writel(val, vpu->enc_base + reg); in vepu_write()
348 static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg) in vepu_read() argument
350 u32 val = readl(vpu->enc_base + reg); in vepu_read()
356 static inline void vdpu_write_relaxed(struct hantro_dev *vpu, in vdpu_write_relaxed() argument
360 writel_relaxed(val, vpu->dec_base + reg); in vdpu_write_relaxed()
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| D | hantro_g1_mpeg2_dec.c | 81 hantro_g1_mpeg2_dec_set_quantisation(struct hantro_dev *vpu, in hantro_g1_mpeg2_dec_set_quantisation() argument
88 vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma, G1_REG_QTABLE_BASE); in hantro_g1_mpeg2_dec_set_quantisation()
92 hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx, in hantro_g1_mpeg2_dec_set_buffers() argument
111 vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE); in hantro_g1_mpeg2_dec_set_buffers()
119 vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE); in hantro_g1_mpeg2_dec_set_buffers()
133 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
134 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
136 vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
137 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE); in hantro_g1_mpeg2_dec_set_buffers()
139 vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE); in hantro_g1_mpeg2_dec_set_buffers()
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| D | rockchip_vpu2_hw_h264_dec.c | 199 struct hantro_dev *vpu = ctx->dev; in set_params() local
207 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); in set_params()
211 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); in set_params()
216 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); in set_params()
219 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); in set_params()
227 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); in set_params()
233 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); in set_params()
248 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); in set_params()
253 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); in set_params()
256 vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65)); in set_params()
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| D | hantro_hevc.c | 75 struct hantro_dev *vpu = ctx->dev; in hantro_hevc_ref_free() local
80 dma_free_coherent(vpu->dev, hevc_dec->ref_bufs[i].size, in hantro_hevc_ref_free()
113 struct hantro_dev *vpu = ctx->dev; in hantro_hevc_get_ref_buf() local
122 dma_alloc_coherent(vpu->dev, in hantro_hevc_get_ref_buf()
161 struct hantro_dev *vpu = ctx->dev; in tile_buffer_reallocate() local
176 dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size, in tile_buffer_reallocate()
183 dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size, in tile_buffer_reallocate()
190 dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size, in tile_buffer_reallocate()
197 hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
205 hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size, in tile_buffer_reallocate()
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| D | Makefile | 3 obj-$(CONFIG_VIDEO_HANTRO) += hantro-vpu.o
5 hantro-vpu-y += \
25 hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \
28 hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \
31 hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
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| /Linux-v5.15/drivers/remoteproc/ |
| D | ingenic_rproc.c | 61 struct vpu { struct
71 struct vpu *vpu = rproc->priv; in ingenic_rproc_prepare() argument
75 ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_prepare()
77 dev_err(vpu->dev, "Unable to start clocks: %d\n", ret); in ingenic_rproc_prepare()
84 struct vpu *vpu = rproc->priv; in ingenic_rproc_unprepare() local
86 clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks); in ingenic_rproc_unprepare()
93 struct vpu *vpu = rproc->priv; in ingenic_rproc_start() local
96 enable_irq(vpu->irq); in ingenic_rproc_start()
100 writel(ctrl, vpu->aux_base + REG_AUX_CTRL); in ingenic_rproc_start()
107 struct vpu *vpu = rproc->priv; in ingenic_rproc_stop() local
[all …]
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| /Linux-v5.15/drivers/media/platform/mtk-mdp/ |
| D | mtk_mdp_vpu.c | 13 static inline struct mtk_mdp_ctx *vpu_to_ctx(struct mtk_mdp_vpu *vpu) in vpu_to_ctx() argument
15 return container_of(vpu, struct mtk_mdp_ctx, vpu); in vpu_to_ctx()
20 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_handle_init_ack() local
24 vpu->vsi = (struct mdp_process_vsi *) in mtk_mdp_vpu_handle_init_ack()
25 vpu_mapping_dm_addr(vpu->pdev, msg->vpu_inst_addr); in mtk_mdp_vpu_handle_init_ack()
26 vpu->inst_addr = msg->vpu_inst_addr; in mtk_mdp_vpu_handle_init_ack()
34 struct mtk_mdp_vpu *vpu = (struct mtk_mdp_vpu *) in mtk_mdp_vpu_ipi_handler() local
38 vpu->failure = msg->status; in mtk_mdp_vpu_ipi_handler()
39 if (!vpu->failure) { in mtk_mdp_vpu_ipi_handler()
48 ctx = vpu_to_ctx(vpu); in mtk_mdp_vpu_ipi_handler()
[all …]
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| D | mtk_mdp_regs.c | 51 struct mdp_buffer *src_buf = &ctx->vpu.vsi->src_buffer; in mtk_mdp_hw_set_input_addr()
61 struct mdp_buffer *dst_buf = &ctx->vpu.vsi->dst_buffer; in mtk_mdp_hw_set_output_addr()
71 struct mdp_config *config = &ctx->vpu.vsi->src_config; in mtk_mdp_hw_set_in_size()
92 struct mdp_config *config = &ctx->vpu.vsi->src_config; in mtk_mdp_hw_set_in_image_format()
93 struct mdp_buffer *src_buf = &ctx->vpu.vsi->src_buffer; in mtk_mdp_hw_set_in_image_format()
107 struct mdp_config *config = &ctx->vpu.vsi->dst_config; in mtk_mdp_hw_set_out_size()
123 struct mdp_config *config = &ctx->vpu.vsi->dst_config; in mtk_mdp_hw_set_out_image_format()
124 struct mdp_buffer *dst_buf = &ctx->vpu.vsi->dst_buffer; in mtk_mdp_hw_set_out_image_format()
136 struct mdp_config_misc *misc = &ctx->vpu.vsi->misc; in mtk_mdp_hw_set_rotation()
145 struct mdp_config_misc *misc = &ctx->vpu.vsi->misc; in mtk_mdp_hw_set_global_alpha()
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