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Searched refs:vm_manager (Results 1 – 25 of 45) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ids.c202 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
218 struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ? in amdgpu_vmid_grab_idle()
229 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
230 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
297 if (adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_reserved()
347 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
375 if (needs_flush && !adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_used()
415 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
477 id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_alloc_reserved()
504 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_free_reserved()
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Damdgpu_vm.c111 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid)); in amdgpu_vm_set_pasid()
119 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm, in amdgpu_vm_set_pasid()
174 adev->vm_manager.block_size; in amdgpu_vm_level_shift()
195 adev->vm_manager.root_level); in amdgpu_vm_num_entries()
197 if (level == adev->vm_manager.root_level) in amdgpu_vm_num_entries()
199 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) in amdgpu_vm_num_entries()
221 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); in amdgpu_vm_num_ats_entries()
237 if (level <= adev->vm_manager.root_level) in amdgpu_vm_entries_mask()
441 cursor->level = adev->vm_manager.root_level; in amdgpu_vm_pt_start()
797 unsigned level = adev->vm_manager.root_level; in amdgpu_vm_clear_bo()
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Damdgpu_vm.h52 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
367 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
368 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
369 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
Dgmc_v6_0.c446 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
505 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
529 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
550 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
877 adev->vm_manager.first_kfd_vmid = 8; in gmc_v6_0_sw_init()
885 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
887 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
Dgfxhub_v1_0.c256 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
257 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
302 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
305 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
Dgfxhub_v2_0.c294 adev->vm_manager.num_level); in gfxhub_v2_0_setup_vmid_config()
311 adev->vm_manager.block_size - 9); in gfxhub_v2_0_setup_vmid_config()
324 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
327 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
Dgfxhub_v2_1.c303 adev->vm_manager.num_level); in gfxhub_v2_1_setup_vmid_config()
320 adev->vm_manager.block_size - 9); in gfxhub_v2_1_setup_vmid_config()
333 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
336 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
Dmmhub_v2_0.c378 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
396 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
409 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
412 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
Dmmhub_v2_3.c291 adev->vm_manager.num_level); in mmhub_v2_3_setup_vmid_config()
309 adev->vm_manager.block_size - 9); in mmhub_v2_3_setup_vmid_config()
322 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
325 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
Dgmc_v7_0.c579 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
651 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
680 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
698 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1057 adev->vm_manager.first_kfd_vmid = 8; in gmc_v7_0_sw_init()
1065 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1067 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
Damdgpu_csa.c29 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; in amdgpu_csa_vaddr()
Dmmhub_v1_0.c237 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
238 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
279 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
282 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
Dgmc_v8_0.c796 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
869 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
913 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
938 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1173 adev->vm_manager.first_kfd_vmid = 8; in gmc_v8_0_sw_init()
1181 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1183 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
Damdgpu_amdkfd.c122 ((1 << adev->vm_manager.first_kfd_vmid) - 1), in amdgpu_amdkfd_device_init()
125 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
744 return vmid >= adev->vm_manager.first_kfd_vmid; in amdgpu_amdkfd_is_kfd_vmid()
Dsi_dma.c846 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; in si_dma_set_vm_pte_funcs()
848 adev->vm_manager.vm_pte_scheds[i] = in si_dma_set_vm_pte_funcs()
851 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
Dgmc_v9_0.c1331 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
1334 adev->vm_manager.vram_base_offset += in gmc_v9_0_vram_gtt_location()
1520 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1624 adev->vm_manager.first_kfd_vmid = in gmc_v9_0_sw_init()
Dgmc_v10_0.c757 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v10_0_vram_gtt_location()
760 adev->vm_manager.vram_base_offset += in gmc_v10_0_vram_gtt_location()
959 adev->vm_manager.first_kfd_vmid = 8; in gmc_v10_0_sw_init()
Damdgpu_vm_sdma.c251 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * in amdgpu_vm_sdma_update()
Dmmhub_v1_7.c270 num_level = adev->vm_manager.num_level; in mmhub_v1_7_setup_vmid_config()
271 block_size = adev->vm_manager.block_size; in mmhub_v1_7_setup_vmid_config()
314 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_7_setup_vmid_config()
317 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_7_setup_vmid_config()
Dsdma_v2_4.c1272 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; in sdma_v2_4_set_vm_pte_funcs()
1274 adev->vm_manager.vm_pte_scheds[i] = in sdma_v2_4_set_vm_pte_funcs()
1277 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v2_4_set_vm_pte_funcs()
Damdgpu_gmc.c748 u64 vram_addr = adev->vm_manager.vram_base_offset - in amdgpu_gmc_init_pdb0()
784 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; in amdgpu_gmc_vram_mc2pa()
Dcik_sdma.c1382 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; in cik_sdma_set_vm_pte_funcs()
1384 adev->vm_manager.vm_pte_scheds[i] = in cik_sdma_set_vm_pte_funcs()
1387 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in cik_sdma_set_vm_pte_funcs()
Dsdma_v5_2.c1826 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v5_2_set_vm_pte_funcs()
1827 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; in sdma_v5_2_set_vm_pte_funcs()
1829 adev->vm_manager.vm_pte_scheds[i] = in sdma_v5_2_set_vm_pte_funcs()
1832 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v5_2_set_vm_pte_funcs()
/Linux-v5.15/drivers/gpu/drm/radeon/
Dradeon_vm.c62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
189 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
196 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
197 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
216 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
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Dni.c1313 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1315 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1350 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2494 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2499 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2501 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()

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