Home
last modified time | relevance | path

Searched refs:vlv_punit_read (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/gt/
Dintel_rps.c1116 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_max_freq()
1143 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); in chv_rps_rpe_freq()
1154 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_guar_freq()
1164 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); in chv_rps_min_freq()
1203 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in chv_rps_enable()
1262 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; in vlv_rps_min_freq()
1304 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_enable()
1533 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_init()
1948 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in read_cagf()
Ddebugfs_gt_pm.c276 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in frequency_show()
/Linux-v5.15/drivers/gpu/drm/i915/
Dintel_sideband.h117 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
Dintel_sideband.c143 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr) in vlv_punit_read() function
Di915_debugfs.c387 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); in i915_frequency_info()
Dintel_pm.c341 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
350 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
364 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
6962 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_wm_get_hw_state()
6975 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
6979 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in vlv_wm_get_hw_state()
6986 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_display_power.c1306 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
1311 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
1320 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
1354 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
1368 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
1871 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1884 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1905 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1910 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_pipe_power_well()
1919 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); in chv_set_pipe_power_well()
[all …]
Dintel_cdclk.c487 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
570 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
574 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
654 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
658 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()