Searched refs:vinst_ctrl (Results 1 – 4 of 4) sorted by relevance
209 config->vinst_ctrl = BIT(0); in reset_store()213 config->vinst_ctrl |= BIT(9); in reset_store()415 config->vinst_ctrl |= BIT(9); in mode_store()417 config->vinst_ctrl &= ~BIT(9); in mode_store()421 config->vinst_ctrl |= BIT(10); in mode_store()423 config->vinst_ctrl &= ~BIT(10); in mode_store()428 config->vinst_ctrl |= BIT(11); in mode_store()430 config->vinst_ctrl &= ~BIT(11); in mode_store()717 val = config->vinst_ctrl & ETMv4_EVENT_MASK; in event_vinst_show()734 config->vinst_ctrl &= ~ETMv4_EVENT_MASK; in event_vinst_store()[all …]
380 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); in etm4_enable_hw()1216 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK; in etm4_set_victlr_access()1217 config->vinst_ctrl |= etm4_get_victlr_access_type(config); in etm4_set_victlr_access()1236 config->vinst_ctrl = BIT(0); in etm4_set_default_config()1345 config->vinst_ctrl |= BIT(9); in etm4_set_default_filter()1449 config->vinst_ctrl |= BIT(9); in etm4_set_event_filters()1477 config->vinst_ctrl |= BIT(9); in etm4_set_event_filters()
64 CHECKREG(TRCVICTLR, vinst_ctrl); in etm4_cfg_map_reg_offset()
775 u32 vinst_ctrl; member862 u32 vinst_ctrl; member
