| /Linux-v5.15/drivers/gpu/drm/i915/ |
| D | intel_uncore.c | 115 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); in fw_domain_arm_timer()
116 d->uncore->fw_domains_timer |= d->mask; in fw_domain_arm_timer()
153 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ in fw_domain_wait_ack_clear()
230 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ in fw_domain_wait_ack_set()
251 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) in fw_domains_get() argument
256 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); in fw_domains_get()
258 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { in fw_domains_get()
263 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) in fw_domains_get()
266 uncore->fw_domains_active |= fw_domains; in fw_domains_get()
270 fw_domains_get_with_fallback(struct intel_uncore *uncore, in fw_domains_get_with_fallback() argument
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| D | vlv_suspend.c | 108 struct intel_uncore *uncore = &i915->uncore; in vlv_save_gunit_s0ix_state() local
115 s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
116 s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
117 s->arb_mode = intel_uncore_read(uncore, ARB_MODE); in vlv_save_gunit_s0ix_state()
118 s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
119 s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
122 s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i)); in vlv_save_gunit_s0ix_state()
124 s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
125 s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
127 s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
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| D | intel_uncore.h | 88 void (*force_wake_get)(struct intel_uncore *uncore,
90 void (*force_wake_put)(struct intel_uncore *uncore,
93 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
95 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
98 u8 (*mmio_readb)(struct intel_uncore *uncore,
100 u16 (*mmio_readw)(struct intel_uncore *uncore,
102 u32 (*mmio_readl)(struct intel_uncore *uncore,
104 u64 (*mmio_readq)(struct intel_uncore *uncore,
107 void (*mmio_writeb)(struct intel_uncore *uncore,
109 void (*mmio_writew)(struct intel_uncore *uncore,
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| D | i915_irq.c | 232 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, in gen3_irq_reset() argument
235 intel_uncore_write(uncore, imr, 0xffffffff); in gen3_irq_reset()
236 intel_uncore_posting_read(uncore, imr); in gen3_irq_reset()
238 intel_uncore_write(uncore, ier, 0); in gen3_irq_reset()
241 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
242 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
243 intel_uncore_write(uncore, iir, 0xffffffff); in gen3_irq_reset()
244 intel_uncore_posting_read(uncore, iir); in gen3_irq_reset()
247 void gen2_irq_reset(struct intel_uncore *uncore) in gen2_irq_reset() argument
249 intel_uncore_write16(uncore, GEN2_IMR, 0xffff); in gen2_irq_reset()
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| D | i915_irq.h | 123 void gen2_irq_reset(struct intel_uncore *uncore);
124 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
127 void gen2_irq_init(struct intel_uncore *uncore,
129 void gen3_irq_init(struct intel_uncore *uncore,
134 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \ argument
137 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
141 #define GEN3_IRQ_RESET(uncore, type) \ argument
142 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
144 #define GEN2_IRQ_RESET(uncore) \ argument
145 gen2_irq_reset(uncore)
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| D | intel_sideband.c | 97 struct intel_uncore *uncore = &i915->uncore; in vlv_sideband_rw() local
106 if (intel_wait_for_register(uncore, in vlv_sideband_rw()
116 intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr); in vlv_sideband_rw()
117 intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val); in vlv_sideband_rw()
118 intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ, in vlv_sideband_rw()
126 if (__intel_wait_for_register_fw(uncore, in vlv_sideband_rw()
130 *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA); in vlv_sideband_rw()
292 struct intel_uncore *uncore = &i915->uncore; in intel_sbi_rw() local
297 if (intel_wait_for_register_fw(uncore, in intel_sbi_rw()
305 intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16); in intel_sbi_rw()
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| D | i915_debugfs.c | 358 struct intel_uncore *uncore = &dev_priv->uncore; in i915_frequency_info() local
365 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); in i915_frequency_info()
366 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); in i915_frequency_info()
377 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); in i915_frequency_info()
422 rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS); in i915_frequency_info()
424 rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP); in i915_frequency_info()
425 gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS); in i915_frequency_info()
427 rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP); in i915_frequency_info()
428 gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS); in i915_frequency_info()
432 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); in i915_frequency_info()
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| D | intel_pm.c | 89 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in gen9_init_clock_gating()
90 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | in gen9_init_clock_gating()
100 intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe), in gen9_init_clock_gating()
105 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1, in gen9_init_clock_gating()
106 intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
109 intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, in gen9_init_clock_gating()
110 intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
116 …intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_… in gen9_init_clock_gating()
125 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in bxt_init_clock_gating()
132 …intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGC… in bxt_init_clock_gating()
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| /Linux-v5.15/drivers/gpu/drm/i915/gt/ |
| D | intel_rc6.c | 43 return rc6_to_gt(rc)->uncore; in rc6_to_uncore()
51 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) in set() argument
53 intel_uncore_write_fw(uncore, reg, val); in set()
59 struct intel_uncore *uncore = gt->uncore; in gen11_rc6_enable() local
70 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); in gen11_rc6_enable()
71 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); in gen11_rc6_enable()
73 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen11_rc6_enable()
74 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen11_rc6_enable()
76 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); in gen11_rc6_enable()
78 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); in gen11_rc6_enable()
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| D | intel_gt_irq.c | 27 void __iomem * const regs = gt->uncore->regs; in gen11_gt_engine_identity()
112 void __iomem * const regs = gt->uncore->regs; in gen11_gt_bank_handler()
147 void __iomem * const regs = gt->uncore->regs; in gen11_gt_reset_one_iir()
176 struct intel_uncore *uncore = gt->uncore; in gen11_gt_irq_reset() local
179 intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); in gen11_gt_irq_reset()
180 intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); in gen11_gt_irq_reset()
183 intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); in gen11_gt_irq_reset()
184 intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0); in gen11_gt_irq_reset()
185 intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0); in gen11_gt_irq_reset()
186 intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0); in gen11_gt_irq_reset()
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| D | debugfs_gt_pm.c | 25 struct intel_uncore *uncore = gt->uncore; in fw_domains_show() local
30 uncore->user_forcewake_count); in fw_domains_show()
32 for_each_fw_domain(fw_domain, uncore, tmp) in fw_domains_show()
48 with_intel_runtime_pm(gt->uncore->rpm, wakeref) in print_rc6_res()
50 intel_uncore_read(gt->uncore, reg), in print_rc6_res()
57 struct intel_uncore *uncore = gt->uncore; in vlv_drpc() local
60 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); in vlv_drpc()
61 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); in vlv_drpc()
81 struct intel_uncore *uncore = gt->uncore; in gen6_drpc() local
85 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS); in gen6_drpc()
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| D | intel_gt_clock_utils.c | 10 static u32 read_reference_ts_freq(struct intel_uncore *uncore) in read_reference_ts_freq() argument
12 u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE); in read_reference_ts_freq()
27 static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore, in gen9_get_crystal_clock_freq() argument
47 static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore, in gen11_get_crystal_clock_freq() argument
73 static u32 read_clock_frequency(struct intel_uncore *uncore) in read_clock_frequency() argument
79 if (GRAPHICS_VER(uncore->i915) <= 4) { in read_clock_frequency()
87 return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16; in read_clock_frequency()
88 } else if (GRAPHICS_VER(uncore->i915) <= 8) { in read_clock_frequency()
97 } else if (GRAPHICS_VER(uncore->i915) <= 9) { in read_clock_frequency()
98 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in read_clock_frequency()
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| D | intel_gtt.c | 351 struct intel_uncore *uncore = gt->uncore; in gtt_write_workarounds() local
360 intel_uncore_write(uncore, in gtt_write_workarounds()
364 intel_uncore_write(uncore, in gtt_write_workarounds()
368 intel_uncore_write(uncore, in gtt_write_workarounds()
372 intel_uncore_write(uncore, in gtt_write_workarounds()
389 intel_uncore_rmw(uncore, in gtt_write_workarounds()
407 intel_uncore_write(uncore, in gtt_write_workarounds()
411 intel_uncore_read(uncore, in gtt_write_workarounds()
416 static void tgl_setup_private_ppat(struct intel_uncore *uncore) in tgl_setup_private_ppat() argument
419 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB); in tgl_setup_private_ppat()
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| D | intel_gt.c | 28 gt->uncore = &i915->uncore; in intel_gt_init_early()
135 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_init_mmio()
148 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_init_mmio()
159 struct intel_uncore *uncore = gt->uncore; in init_unused_ring() local
161 intel_uncore_write(uncore, RING_CTL(base), 0); in init_unused_ring()
162 intel_uncore_write(uncore, RING_HEAD(base), 0); in init_unused_ring()
163 intel_uncore_write(uncore, RING_TAIL(base), 0); in init_unused_ring()
164 intel_uncore_write(uncore, RING_START(base), 0); in init_unused_ring()
189 struct intel_uncore *uncore = gt->uncore; in intel_gt_init_hw() local
195 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); in intel_gt_init_hw()
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| D | intel_rps.c | 37 return rps_to_gt(rps)->uncore; in rps_to_uncore()
59 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val) in set() argument
61 intel_uncore_write_fw(uncore, reg, val); in set()
195 intel_uncore_write(gt->uncore, in rps_enable_interrupts()
228 intel_uncore_write(gt->uncore, in rps_disable_interrupts()
266 struct intel_uncore *uncore = rps_to_uncore(rps); in gen5_rps_init() local
286 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); in gen5_rps_init()
304 struct intel_uncore *uncore = in __ips_chipset_val() local
323 total = intel_uncore_read(uncore, DMIEC); in __ips_chipset_val()
324 total += intel_uncore_read(uncore, DDREC); in __ips_chipset_val()
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| D | intel_ggtt_fencing.c | 50 return fence->ggtt->vm.gt->uncore; in fence_to_uncore()
86 struct intel_uncore *uncore = fence_to_uncore(fence); in i965_write_fence_reg() local
98 intel_uncore_write_fw(uncore, fence_reg_lo, 0); in i965_write_fence_reg()
99 intel_uncore_posting_read_fw(uncore, fence_reg_lo); in i965_write_fence_reg()
101 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val)); in i965_write_fence_reg()
102 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val)); in i965_write_fence_reg()
103 intel_uncore_posting_read_fw(uncore, fence_reg_lo); in i965_write_fence_reg()
133 struct intel_uncore *uncore = fence_to_uncore(fence); in i915_write_fence_reg() local
136 intel_uncore_write_fw(uncore, reg, val); in i915_write_fence_reg()
137 intel_uncore_posting_read_fw(uncore, reg); in i915_write_fence_reg()
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| D | intel_gt_pm_irq.c | 15 struct intel_uncore *uncore = gt->uncore; in write_pm_imr() local
28 intel_uncore_write(uncore, reg, mask); in write_pm_imr()
63 struct intel_uncore *uncore = gt->uncore; in gen6_gt_pm_reset_iir() local
68 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
69 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
70 intel_uncore_posting_read(uncore, reg); in gen6_gt_pm_reset_iir()
76 struct intel_uncore *uncore = gt->uncore; in write_pm_ier() local
89 intel_uncore_write(uncore, reg, mask); in write_pm_ier()
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| D | intel_sseu_debugfs.c | 23 struct intel_uncore *uncore = gt->uncore; in cherryview_sseu_device_status() local
28 sig1[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG1); in cherryview_sseu_device_status()
29 sig1[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG1); in cherryview_sseu_device_status()
30 sig2[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG2); in cherryview_sseu_device_status()
31 sig2[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG2); in cherryview_sseu_device_status()
57 struct intel_uncore *uncore = gt->uncore; in gen11_sseu_device_status() local
69 s_reg[s] = intel_uncore_read(uncore, GEN10_SLICE_PGCTL_ACK(s)) & in gen11_sseu_device_status()
71 eu_reg[2 * s] = intel_uncore_read(uncore, in gen11_sseu_device_status()
73 eu_reg[2 * s + 1] = intel_uncore_read(uncore, in gen11_sseu_device_status()
117 struct intel_uncore *uncore = gt->uncore; in gen9_sseu_device_status() local
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| /Linux-v5.15/drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_fw.c | 16 static void guc_prepare_xfer(struct intel_uncore *uncore) in guc_prepare_xfer() argument
26 intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags); in guc_prepare_xfer()
28 if (IS_GEN9_LP(uncore->i915)) in guc_prepare_xfer()
29 intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
31 intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); in guc_prepare_xfer()
33 if (GRAPHICS_VER(uncore->i915) == 9) { in guc_prepare_xfer()
35 intel_uncore_rmw(uncore, GEN7_MISCCPCTL, in guc_prepare_xfer()
39 intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF); in guc_prepare_xfer()
45 struct intel_uncore *uncore) in guc_xfer_rsa() argument
55 intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]); in guc_xfer_rsa()
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| D | intel_guc.c | 46 intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER); in intel_guc_notify()
68 fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore, in intel_guc_init_send_regs()
93 WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & in gen9_enable_guc_interrupts()
131 intel_uncore_write(gt->uncore, in gen11_enable_guc_interrupts()
133 intel_uncore_write(gt->uncore, in gen11_enable_guc_interrupts()
144 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0); in gen11_disable_guc_interrupts()
145 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0); in gen11_disable_guc_interrupts()
290 struct intel_uncore *uncore = guc_to_gt(guc)->uncore; in intel_guc_write_params() local
298 intel_uncore_forcewake_get(uncore, FORCEWAKE_GT); in intel_guc_write_params()
300 intel_uncore_write(uncore, SOFT_SCRATCH(0), 0); in intel_guc_write_params()
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| /Linux-v5.15/drivers/gpu/drm/i915/selftests/ |
| D | intel_uncore.c | 149 struct intel_uncore *uncore = gt->uncore; in live_forcewake_ops() local
185 wakeref = intel_runtime_pm_get(uncore->rpm); in live_forcewake_ops()
187 for_each_fw_domain(domain, uncore, tmp) { in live_forcewake_ops()
197 u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset; in live_forcewake_ops()
204 fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio, in live_forcewake_ops()
209 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { in live_forcewake_ops()
219 intel_uncore_forcewake_get(uncore, fw_domains); in live_forcewake_ops()
221 intel_uncore_forcewake_put(uncore, fw_domains); in live_forcewake_ops()
224 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { in live_forcewake_ops()
256 intel_runtime_pm_put(uncore->rpm, wakeref); in live_forcewake_ops()
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| D | mock_uncore.c | 29 nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
36 nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
42 void mock_uncore_init(struct intel_uncore *uncore, in mock_uncore_init() argument
45 intel_uncore_init_early(uncore, i915); in mock_uncore_init()
47 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop); in mock_uncore_init()
48 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, nop); in mock_uncore_init()
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| /Linux-v5.15/arch/x86/events/amd/ |
| D | uncore.c | 129 struct amd_uncore *uncore = event_to_amd_uncore(event); in amd_uncore_add() local
133 if (hwc->idx != -1 && uncore->events[hwc->idx] == event) in amd_uncore_add()
136 for (i = 0; i < uncore->num_counters; i++) { in amd_uncore_add()
137 if (uncore->events[i] == event) { in amd_uncore_add()
145 for (i = 0; i < uncore->num_counters; i++) { in amd_uncore_add()
146 if (cmpxchg(&uncore->events[i], NULL, event) == NULL) { in amd_uncore_add()
156 hwc->config_base = uncore->msr_base + (2 * hwc->idx); in amd_uncore_add()
157 hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); in amd_uncore_add()
158 hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx; in amd_uncore_add()
170 struct amd_uncore *uncore = event_to_amd_uncore(event); in amd_uncore_del() local
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| /Linux-v5.15/arch/x86/events/intel/ |
| D | uncore_discovery.c | 530 struct intel_uncore_type *uncore, in uncore_update_uncore_type() argument
533 uncore->type_id = type->type; in uncore_update_uncore_type()
534 uncore->num_boxes = type->num_boxes; in uncore_update_uncore_type()
535 uncore->num_counters = type->num_counters; in uncore_update_uncore_type()
536 uncore->perf_ctr_bits = type->counter_width; in uncore_update_uncore_type()
537 uncore->box_ids = type->ids; in uncore_update_uncore_type()
541 uncore->ops = &generic_uncore_msr_ops; in uncore_update_uncore_type()
542 uncore->perf_ctr = (unsigned int)type->box_ctrl + type->ctr_offset; in uncore_update_uncore_type()
543 uncore->event_ctl = (unsigned int)type->box_ctrl + type->ctl_offset; in uncore_update_uncore_type()
544 uncore->box_ctl = (unsigned int)type->box_ctrl; in uncore_update_uncore_type()
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| /Linux-v5.15/drivers/gpu/drm/i915/display/ |
| D | intel_tc.c | 83 struct intel_uncore *uncore = &i915->uncore; in intel_tc_port_get_lane_mask() local
86 lane_mask = intel_uncore_read(uncore, in intel_tc_port_get_lane_mask()
99 struct intel_uncore *uncore = &i915->uncore; in intel_tc_port_get_pin_assignment_mask() local
102 pin_mask = intel_uncore_read(uncore, in intel_tc_port_get_pin_assignment_mask()
149 struct intel_uncore *uncore = &i915->uncore; in intel_tc_port_set_fia_lane_count() local
157 val = intel_uncore_read(uncore, in intel_tc_port_set_fia_lane_count()
179 intel_uncore_write(uncore, in intel_tc_port_set_fia_lane_count()
209 struct intel_uncore *uncore = &i915->uncore; in icl_tc_port_live_status_mask() local
214 val = intel_uncore_read(uncore, in icl_tc_port_live_status_mask()
229 if (intel_uncore_read(uncore, SDEISR) & isr_bit) in icl_tc_port_live_status_mask()
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