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Searched refs:umc_reg_offset (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dumc_v8_7.c51 uint32_t umc_reg_offset) in umc_v8_7_clear_error_count_per_channel() argument
63 umc_reg_offset) * 4); in umc_v8_7_clear_error_count_per_channel()
67 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
71 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
76 umc_reg_offset) * 4); in umc_v8_7_clear_error_count_per_channel()
80 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
84 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
92 uint32_t umc_reg_offset = 0; in umc_v8_7_clear_error_count() local
95 umc_reg_offset = get_umc_8_reg_offset(adev, in umc_v8_7_clear_error_count()
100 umc_reg_offset); in umc_v8_7_clear_error_count()
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Dumc_v6_7.c54 uint32_t umc_reg_offset, in umc_v6_7_query_correctable_error_count() argument
71 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
74 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
76 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
84 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
86 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
93 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
100 uint32_t umc_reg_offset, in umc_v6_7_querry_uncorrectable_error_count() argument
110 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v6_7_querry_uncorrectable_error_count()
121 uint32_t umc_reg_offset) in umc_v6_7_reset_error_count_per_channel() argument
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Dumc_v6_1.c95 uint32_t umc_reg_offset) in umc_v6_1_clear_error_count_per_channel() argument
120 umc_reg_offset) * 4); in umc_v6_1_clear_error_count_per_channel()
124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
128 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
133 umc_reg_offset) * 4); in umc_v6_1_clear_error_count_per_channel()
137 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
141 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
149 uint32_t umc_reg_offset = 0; in umc_v6_1_clear_error_count() local
157 umc_reg_offset = get_umc_6_reg_offset(adev, in umc_v6_1_clear_error_count()
162 umc_reg_offset); in umc_v6_1_clear_error_count()
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