1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // flexcan.c - FLEXCAN CAN controller driver
4 //
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
9 //
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11
12 #include <dt-bindings/firmware/imx/rsrc.h>
13 #include <linux/bitfield.h>
14 #include <linux/can.h>
15 #include <linux/can/dev.h>
16 #include <linux/can/error.h>
17 #include <linux/can/led.h>
18 #include <linux/can/rx-offload.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/firmware/imx/sci.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/platform_device.h>
31 #include <linux/can/platform/flexcan.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/regmap.h>
34 #include <linux/regulator/consumer.h>
35
36 #define DRV_NAME "flexcan"
37
38 /* 8 for RX fifo and 2 error handling */
39 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
40
41 /* FLEXCAN module configuration register (CANMCR) bits */
42 #define FLEXCAN_MCR_MDIS BIT(31)
43 #define FLEXCAN_MCR_FRZ BIT(30)
44 #define FLEXCAN_MCR_FEN BIT(29)
45 #define FLEXCAN_MCR_HALT BIT(28)
46 #define FLEXCAN_MCR_NOT_RDY BIT(27)
47 #define FLEXCAN_MCR_WAK_MSK BIT(26)
48 #define FLEXCAN_MCR_SOFTRST BIT(25)
49 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
50 #define FLEXCAN_MCR_SUPV BIT(23)
51 #define FLEXCAN_MCR_SLF_WAK BIT(22)
52 #define FLEXCAN_MCR_WRN_EN BIT(21)
53 #define FLEXCAN_MCR_LPM_ACK BIT(20)
54 #define FLEXCAN_MCR_WAK_SRC BIT(19)
55 #define FLEXCAN_MCR_DOZE BIT(18)
56 #define FLEXCAN_MCR_SRX_DIS BIT(17)
57 #define FLEXCAN_MCR_IRMQ BIT(16)
58 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
59 #define FLEXCAN_MCR_AEN BIT(12)
60 #define FLEXCAN_MCR_FDEN BIT(11)
61 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
62 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
63 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
64 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
65 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
66 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
67
68 /* FLEXCAN control register (CANCTRL) bits */
69 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
70 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
71 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
72 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
73 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
74 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
75 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
76 #define FLEXCAN_CTRL_LPB BIT(12)
77 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
78 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
79 #define FLEXCAN_CTRL_SMP BIT(7)
80 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
81 #define FLEXCAN_CTRL_TSYN BIT(5)
82 #define FLEXCAN_CTRL_LBUF BIT(4)
83 #define FLEXCAN_CTRL_LOM BIT(3)
84 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
85 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
86 #define FLEXCAN_CTRL_ERR_STATE \
87 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
88 FLEXCAN_CTRL_BOFF_MSK)
89 #define FLEXCAN_CTRL_ERR_ALL \
90 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
91
92 /* FLEXCAN control register 2 (CTRL2) bits */
93 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
94 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
95 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
96 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
97 #define FLEXCAN_CTRL2_MRP BIT(18)
98 #define FLEXCAN_CTRL2_RRS BIT(17)
99 #define FLEXCAN_CTRL2_EACEN BIT(16)
100 #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
101
102 /* FLEXCAN memory error control register (MECR) bits */
103 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
104 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
105 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
106 #define FLEXCAN_MECR_CEI_MSK BIT(16)
107 #define FLEXCAN_MECR_HAERRIE BIT(15)
108 #define FLEXCAN_MECR_FAERRIE BIT(14)
109 #define FLEXCAN_MECR_EXTERRIE BIT(13)
110 #define FLEXCAN_MECR_RERRDIS BIT(9)
111 #define FLEXCAN_MECR_ECCDIS BIT(8)
112 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
113
114 /* FLEXCAN error and status register (ESR) bits */
115 #define FLEXCAN_ESR_TWRN_INT BIT(17)
116 #define FLEXCAN_ESR_RWRN_INT BIT(16)
117 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
118 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
119 #define FLEXCAN_ESR_ACK_ERR BIT(13)
120 #define FLEXCAN_ESR_CRC_ERR BIT(12)
121 #define FLEXCAN_ESR_FRM_ERR BIT(11)
122 #define FLEXCAN_ESR_STF_ERR BIT(10)
123 #define FLEXCAN_ESR_TX_WRN BIT(9)
124 #define FLEXCAN_ESR_RX_WRN BIT(8)
125 #define FLEXCAN_ESR_IDLE BIT(7)
126 #define FLEXCAN_ESR_TXRX BIT(6)
127 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
128 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
129 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_BOFF_INT BIT(2)
132 #define FLEXCAN_ESR_ERR_INT BIT(1)
133 #define FLEXCAN_ESR_WAK_INT BIT(0)
134 #define FLEXCAN_ESR_ERR_BUS \
135 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
136 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
137 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
138 #define FLEXCAN_ESR_ERR_STATE \
139 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
140 #define FLEXCAN_ESR_ERR_ALL \
141 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
142 #define FLEXCAN_ESR_ALL_INT \
143 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
144 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
145
146 /* FLEXCAN Bit Timing register (CBT) bits */
147 #define FLEXCAN_CBT_BTF BIT(31)
148 #define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21)
149 #define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16)
150 #define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10)
151 #define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5)
152 #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
153
154 /* FLEXCAN FD control register (FDCTRL) bits */
155 #define FLEXCAN_FDCTRL_FDRATE BIT(31)
156 #define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19)
157 #define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16)
158 #define FLEXCAN_FDCTRL_MBDSR_8 0x0
159 #define FLEXCAN_FDCTRL_MBDSR_12 0x1
160 #define FLEXCAN_FDCTRL_MBDSR_32 0x2
161 #define FLEXCAN_FDCTRL_MBDSR_64 0x3
162 #define FLEXCAN_FDCTRL_TDCEN BIT(15)
163 #define FLEXCAN_FDCTRL_TDCFAIL BIT(14)
164 #define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8)
165 #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
166
167 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
168 #define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20)
169 #define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16)
170 #define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10)
171 #define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5)
172 #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
173
174 /* FLEXCAN interrupt flag register (IFLAG) bits */
175 /* Errata ERR005829 step7: Reserve first valid MB */
176 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
177 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
178 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
179 #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
180 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
181 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
182 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
183
184 /* FLEXCAN message buffers */
185 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
186 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
187 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
188 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
189 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
190 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
191 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
192
193 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
194 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
195 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
196 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
197
198 #define FLEXCAN_MB_CNT_EDL BIT(31)
199 #define FLEXCAN_MB_CNT_BRS BIT(30)
200 #define FLEXCAN_MB_CNT_ESI BIT(29)
201 #define FLEXCAN_MB_CNT_SRR BIT(22)
202 #define FLEXCAN_MB_CNT_IDE BIT(21)
203 #define FLEXCAN_MB_CNT_RTR BIT(20)
204 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
205 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
206
207 #define FLEXCAN_TIMEOUT_US (250)
208
209 /* FLEXCAN hardware feature flags
210 *
211 * Below is some version info we got:
212 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode MB
213 * Filter? connected? Passive detection ption in MB Supported?
214 * MCF5441X FlexCAN2 ? no yes no no yes no 16
215 * MX25 FlexCAN2 03.00.00.00 no no no no no no 64
216 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no 64
217 * MX35 FlexCAN2 03.00.00.00 no no no no no no 64
218 * MX53 FlexCAN2 03.00.00.00 yes no no no no no 64
219 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no 64
220 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 64
221 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes 64
222 * VF610 FlexCAN3 ? no yes no yes yes? no 64
223 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no 64
224 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes 64
225 *
226 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
227 */
228
229 /* [TR]WRN_INT not connected */
230 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)
231 /* Disable RX FIFO Global mask */
232 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)
233 /* Enable EACEN and RRS bit in ctrl2 */
234 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)
235 /* Disable non-correctable errors interrupt and freeze mode */
236 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)
237 /* Use timestamp based offloading */
238 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)
239 /* No interrupt for error passive */
240 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)
241 /* default to BE register access */
242 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)
243 /* Setup stop mode with GPR to support wakeup */
244 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)
245 /* Support CAN-FD mode */
246 #define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)
247 /* support memory detection and correction */
248 #define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)
249 /* Setup stop mode with SCU firmware to support wakeup */
250 #define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)
251 /* Setup 3 separate interrupts, main, boff and err */
252 #define FLEXCAN_QUIRK_NR_IRQ_3 BIT(12)
253 /* Setup 16 mailboxes */
254 #define FLEXCAN_QUIRK_NR_MB_16 BIT(13)
255
256 /* Structure of the message buffer */
257 struct flexcan_mb {
258 u32 can_ctrl;
259 u32 can_id;
260 u32 data[];
261 };
262
263 /* Structure of the hardware registers */
264 struct flexcan_regs {
265 u32 mcr; /* 0x00 */
266 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
267 u32 timer; /* 0x08 */
268 u32 tcr; /* 0x0c */
269 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
270 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
271 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
272 u32 ecr; /* 0x1c */
273 u32 esr; /* 0x20 */
274 u32 imask2; /* 0x24 */
275 u32 imask1; /* 0x28 */
276 u32 iflag2; /* 0x2c */
277 u32 iflag1; /* 0x30 */
278 union { /* 0x34 */
279 u32 gfwr_mx28; /* MX28, MX53 */
280 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
281 };
282 u32 esr2; /* 0x38 */
283 u32 imeur; /* 0x3c */
284 u32 lrfr; /* 0x40 */
285 u32 crcr; /* 0x44 */
286 u32 rxfgmask; /* 0x48 */
287 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
288 u32 cbt; /* 0x50 - Not affected by Soft Reset */
289 u32 _reserved2; /* 0x54 */
290 u32 dbg1; /* 0x58 */
291 u32 dbg2; /* 0x5c */
292 u32 _reserved3[8]; /* 0x60 */
293 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
294 /* FIFO-mode:
295 * MB
296 * 0x080...0x08f 0 RX message buffer
297 * 0x090...0x0df 1-5 reserved
298 * 0x0e0...0x0ff 6-7 8 entry ID table
299 * (mx25, mx28, mx35, mx53)
300 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
301 * size conf'ed via ctrl2::RFFN
302 * (mx6, vf610)
303 */
304 u32 _reserved4[256]; /* 0x480 */
305 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
306 u32 _reserved5[24]; /* 0x980 */
307 u32 gfwr_mx6; /* 0x9e0 - MX6 */
308 u32 _reserved6[39]; /* 0x9e4 */
309 u32 _rxfir[6]; /* 0xa80 */
310 u32 _reserved8[2]; /* 0xa98 */
311 u32 _rxmgmask; /* 0xaa0 */
312 u32 _rxfgmask; /* 0xaa4 */
313 u32 _rx14mask; /* 0xaa8 */
314 u32 _rx15mask; /* 0xaac */
315 u32 tx_smb[4]; /* 0xab0 */
316 u32 rx_smb0[4]; /* 0xac0 */
317 u32 rx_smb1[4]; /* 0xad0 */
318 u32 mecr; /* 0xae0 */
319 u32 erriar; /* 0xae4 */
320 u32 erridpr; /* 0xae8 */
321 u32 errippr; /* 0xaec */
322 u32 rerrar; /* 0xaf0 */
323 u32 rerrdr; /* 0xaf4 */
324 u32 rerrsynr; /* 0xaf8 */
325 u32 errsr; /* 0xafc */
326 u32 _reserved7[64]; /* 0xb00 */
327 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
328 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
329 u32 fdcrc; /* 0xc08 */
330 u32 _reserved9[199]; /* 0xc0c */
331 u32 tx_smb_fd[18]; /* 0xf28 */
332 u32 rx_smb0_fd[18]; /* 0xf70 */
333 u32 rx_smb1_fd[18]; /* 0xfb8 */
334 };
335
336 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
337
338 struct flexcan_devtype_data {
339 u32 quirks; /* quirks needed for different IP cores */
340 };
341
342 struct flexcan_stop_mode {
343 struct regmap *gpr;
344 u8 req_gpr;
345 u8 req_bit;
346 };
347
348 struct flexcan_priv {
349 struct can_priv can;
350 struct can_rx_offload offload;
351 struct device *dev;
352
353 struct flexcan_regs __iomem *regs;
354 struct flexcan_mb __iomem *tx_mb;
355 struct flexcan_mb __iomem *tx_mb_reserved;
356 u8 tx_mb_idx;
357 u8 mb_count;
358 u8 mb_size;
359 u8 clk_src; /* clock source of CAN Protocol Engine */
360 u8 scu_idx;
361
362 u64 rx_mask;
363 u64 tx_mask;
364 u32 reg_ctrl_default;
365
366 struct clk *clk_ipg;
367 struct clk *clk_per;
368 const struct flexcan_devtype_data *devtype_data;
369 struct regulator *reg_xceiver;
370 struct flexcan_stop_mode stm;
371
372 int irq_boff;
373 int irq_err;
374
375 /* IPC handle when setup stop mode by System Controller firmware(scfw) */
376 struct imx_sc_ipc *sc_ipc_handle;
377
378 /* Read and Write APIs */
379 u32 (*read)(void __iomem *addr);
380 void (*write)(u32 val, void __iomem *addr);
381 };
382
383 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
384 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
385 FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16,
386 };
387
388 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
389 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
390 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
391 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
392 };
393
394 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
395 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
396 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
397 };
398
399 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
400 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
401 };
402
403 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
404 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
405 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
406 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR,
407 };
408
409 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
410 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
411 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
412 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW,
413 };
414
415 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
416 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
417 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
418 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
419 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC,
420 };
421
422 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
423 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
424 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
425 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
426 };
427
428 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
429 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
430 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
431 };
432
433 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
434 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
435 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
436 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_SUPPORT_FD |
437 FLEXCAN_QUIRK_SUPPORT_ECC,
438 };
439
440 static const struct can_bittiming_const flexcan_bittiming_const = {
441 .name = DRV_NAME,
442 .tseg1_min = 4,
443 .tseg1_max = 16,
444 .tseg2_min = 2,
445 .tseg2_max = 8,
446 .sjw_max = 4,
447 .brp_min = 1,
448 .brp_max = 256,
449 .brp_inc = 1,
450 };
451
452 static const struct can_bittiming_const flexcan_fd_bittiming_const = {
453 .name = DRV_NAME,
454 .tseg1_min = 2,
455 .tseg1_max = 96,
456 .tseg2_min = 2,
457 .tseg2_max = 32,
458 .sjw_max = 16,
459 .brp_min = 1,
460 .brp_max = 1024,
461 .brp_inc = 1,
462 };
463
464 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = {
465 .name = DRV_NAME,
466 .tseg1_min = 2,
467 .tseg1_max = 39,
468 .tseg2_min = 2,
469 .tseg2_max = 8,
470 .sjw_max = 4,
471 .brp_min = 1,
472 .brp_max = 1024,
473 .brp_inc = 1,
474 };
475
476 /* FlexCAN module is essentially modelled as a little-endian IP in most
477 * SoCs, i.e the registers as well as the message buffer areas are
478 * implemented in a little-endian fashion.
479 *
480 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
481 * module in a big-endian fashion (i.e the registers as well as the
482 * message buffer areas are implemented in a big-endian way).
483 *
484 * In addition, the FlexCAN module can be found on SoCs having ARM or
485 * PPC cores. So, we need to abstract off the register read/write
486 * functions, ensuring that these cater to all the combinations of module
487 * endianness and underlying CPU endianness.
488 */
flexcan_read_be(void __iomem * addr)489 static inline u32 flexcan_read_be(void __iomem *addr)
490 {
491 return ioread32be(addr);
492 }
493
flexcan_write_be(u32 val,void __iomem * addr)494 static inline void flexcan_write_be(u32 val, void __iomem *addr)
495 {
496 iowrite32be(val, addr);
497 }
498
flexcan_read_le(void __iomem * addr)499 static inline u32 flexcan_read_le(void __iomem *addr)
500 {
501 return ioread32(addr);
502 }
503
flexcan_write_le(u32 val,void __iomem * addr)504 static inline void flexcan_write_le(u32 val, void __iomem *addr)
505 {
506 iowrite32(val, addr);
507 }
508
flexcan_get_mb(const struct flexcan_priv * priv,u8 mb_index)509 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
510 u8 mb_index)
511 {
512 u8 bank_size;
513 bool bank;
514
515 if (WARN_ON(mb_index >= priv->mb_count))
516 return NULL;
517
518 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
519
520 bank = mb_index >= bank_size;
521 if (bank)
522 mb_index -= bank_size;
523
524 return (struct flexcan_mb __iomem *)
525 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
526 }
527
flexcan_low_power_enter_ack(struct flexcan_priv * priv)528 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
529 {
530 struct flexcan_regs __iomem *regs = priv->regs;
531 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
532
533 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
534 udelay(10);
535
536 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
537 return -ETIMEDOUT;
538
539 return 0;
540 }
541
flexcan_low_power_exit_ack(struct flexcan_priv * priv)542 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
543 {
544 struct flexcan_regs __iomem *regs = priv->regs;
545 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
546
547 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
548 udelay(10);
549
550 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
551 return -ETIMEDOUT;
552
553 return 0;
554 }
555
flexcan_enable_wakeup_irq(struct flexcan_priv * priv,bool enable)556 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
557 {
558 struct flexcan_regs __iomem *regs = priv->regs;
559 u32 reg_mcr;
560
561 reg_mcr = priv->read(®s->mcr);
562
563 if (enable)
564 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
565 else
566 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
567
568 priv->write(reg_mcr, ®s->mcr);
569 }
570
flexcan_stop_mode_enable_scfw(struct flexcan_priv * priv,bool enabled)571 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled)
572 {
573 u8 idx = priv->scu_idx;
574 u32 rsrc_id, val;
575
576 rsrc_id = IMX_SC_R_CAN(idx);
577
578 if (enabled)
579 val = 1;
580 else
581 val = 0;
582
583 /* stop mode request via scu firmware */
584 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id,
585 IMX_SC_C_IPG_STOP, val);
586 }
587
flexcan_enter_stop_mode(struct flexcan_priv * priv)588 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
589 {
590 struct flexcan_regs __iomem *regs = priv->regs;
591 u32 reg_mcr;
592 int ret;
593
594 reg_mcr = priv->read(®s->mcr);
595 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
596 priv->write(reg_mcr, ®s->mcr);
597
598 /* enable stop request */
599 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
600 ret = flexcan_stop_mode_enable_scfw(priv, true);
601 if (ret < 0)
602 return ret;
603 } else {
604 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
605 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
606 }
607
608 return flexcan_low_power_enter_ack(priv);
609 }
610
flexcan_exit_stop_mode(struct flexcan_priv * priv)611 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
612 {
613 struct flexcan_regs __iomem *regs = priv->regs;
614 u32 reg_mcr;
615 int ret;
616
617 /* remove stop request */
618 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) {
619 ret = flexcan_stop_mode_enable_scfw(priv, false);
620 if (ret < 0)
621 return ret;
622 } else {
623 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
624 1 << priv->stm.req_bit, 0);
625 }
626
627 reg_mcr = priv->read(®s->mcr);
628 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
629 priv->write(reg_mcr, ®s->mcr);
630
631 return flexcan_low_power_exit_ack(priv);
632 }
633
flexcan_error_irq_enable(const struct flexcan_priv * priv)634 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
635 {
636 struct flexcan_regs __iomem *regs = priv->regs;
637 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
638
639 priv->write(reg_ctrl, ®s->ctrl);
640 }
641
flexcan_error_irq_disable(const struct flexcan_priv * priv)642 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
643 {
644 struct flexcan_regs __iomem *regs = priv->regs;
645 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
646
647 priv->write(reg_ctrl, ®s->ctrl);
648 }
649
flexcan_clks_enable(const struct flexcan_priv * priv)650 static int flexcan_clks_enable(const struct flexcan_priv *priv)
651 {
652 int err = 0;
653
654 if (priv->clk_ipg) {
655 err = clk_prepare_enable(priv->clk_ipg);
656 if (err)
657 return err;
658 }
659
660 if (priv->clk_per) {
661 err = clk_prepare_enable(priv->clk_per);
662 if (err)
663 clk_disable_unprepare(priv->clk_ipg);
664 }
665
666 return err;
667 }
668
flexcan_clks_disable(const struct flexcan_priv * priv)669 static void flexcan_clks_disable(const struct flexcan_priv *priv)
670 {
671 clk_disable_unprepare(priv->clk_per);
672 clk_disable_unprepare(priv->clk_ipg);
673 }
674
flexcan_transceiver_enable(const struct flexcan_priv * priv)675 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
676 {
677 if (!priv->reg_xceiver)
678 return 0;
679
680 return regulator_enable(priv->reg_xceiver);
681 }
682
flexcan_transceiver_disable(const struct flexcan_priv * priv)683 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
684 {
685 if (!priv->reg_xceiver)
686 return 0;
687
688 return regulator_disable(priv->reg_xceiver);
689 }
690
flexcan_chip_enable(struct flexcan_priv * priv)691 static int flexcan_chip_enable(struct flexcan_priv *priv)
692 {
693 struct flexcan_regs __iomem *regs = priv->regs;
694 u32 reg;
695
696 reg = priv->read(®s->mcr);
697 reg &= ~FLEXCAN_MCR_MDIS;
698 priv->write(reg, ®s->mcr);
699
700 return flexcan_low_power_exit_ack(priv);
701 }
702
flexcan_chip_disable(struct flexcan_priv * priv)703 static int flexcan_chip_disable(struct flexcan_priv *priv)
704 {
705 struct flexcan_regs __iomem *regs = priv->regs;
706 u32 reg;
707
708 reg = priv->read(®s->mcr);
709 reg |= FLEXCAN_MCR_MDIS;
710 priv->write(reg, ®s->mcr);
711
712 return flexcan_low_power_enter_ack(priv);
713 }
714
flexcan_chip_freeze(struct flexcan_priv * priv)715 static int flexcan_chip_freeze(struct flexcan_priv *priv)
716 {
717 struct flexcan_regs __iomem *regs = priv->regs;
718 unsigned int timeout;
719 u32 bitrate = priv->can.bittiming.bitrate;
720 u32 reg;
721
722 if (bitrate)
723 timeout = 1000 * 1000 * 10 / bitrate;
724 else
725 timeout = FLEXCAN_TIMEOUT_US / 10;
726
727 reg = priv->read(®s->mcr);
728 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT;
729 priv->write(reg, ®s->mcr);
730
731 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
732 udelay(100);
733
734 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
735 return -ETIMEDOUT;
736
737 return 0;
738 }
739
flexcan_chip_unfreeze(struct flexcan_priv * priv)740 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
741 {
742 struct flexcan_regs __iomem *regs = priv->regs;
743 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
744 u32 reg;
745
746 reg = priv->read(®s->mcr);
747 reg &= ~FLEXCAN_MCR_HALT;
748 priv->write(reg, ®s->mcr);
749
750 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
751 udelay(10);
752
753 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
754 return -ETIMEDOUT;
755
756 return 0;
757 }
758
flexcan_chip_softreset(struct flexcan_priv * priv)759 static int flexcan_chip_softreset(struct flexcan_priv *priv)
760 {
761 struct flexcan_regs __iomem *regs = priv->regs;
762 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
763
764 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
765 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
766 udelay(10);
767
768 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
769 return -ETIMEDOUT;
770
771 return 0;
772 }
773
__flexcan_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)774 static int __flexcan_get_berr_counter(const struct net_device *dev,
775 struct can_berr_counter *bec)
776 {
777 const struct flexcan_priv *priv = netdev_priv(dev);
778 struct flexcan_regs __iomem *regs = priv->regs;
779 u32 reg = priv->read(®s->ecr);
780
781 bec->txerr = (reg >> 0) & 0xff;
782 bec->rxerr = (reg >> 8) & 0xff;
783
784 return 0;
785 }
786
flexcan_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)787 static int flexcan_get_berr_counter(const struct net_device *dev,
788 struct can_berr_counter *bec)
789 {
790 const struct flexcan_priv *priv = netdev_priv(dev);
791 int err;
792
793 err = pm_runtime_get_sync(priv->dev);
794 if (err < 0) {
795 pm_runtime_put_noidle(priv->dev);
796 return err;
797 }
798
799 err = __flexcan_get_berr_counter(dev, bec);
800
801 pm_runtime_put(priv->dev);
802
803 return err;
804 }
805
flexcan_start_xmit(struct sk_buff * skb,struct net_device * dev)806 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
807 {
808 const struct flexcan_priv *priv = netdev_priv(dev);
809 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
810 u32 can_id;
811 u32 data;
812 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16);
813 int i;
814
815 if (can_dropped_invalid_skb(dev, skb))
816 return NETDEV_TX_OK;
817
818 netif_stop_queue(dev);
819
820 if (cfd->can_id & CAN_EFF_FLAG) {
821 can_id = cfd->can_id & CAN_EFF_MASK;
822 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
823 } else {
824 can_id = (cfd->can_id & CAN_SFF_MASK) << 18;
825 }
826
827 if (cfd->can_id & CAN_RTR_FLAG)
828 ctrl |= FLEXCAN_MB_CNT_RTR;
829
830 if (can_is_canfd_skb(skb)) {
831 ctrl |= FLEXCAN_MB_CNT_EDL;
832
833 if (cfd->flags & CANFD_BRS)
834 ctrl |= FLEXCAN_MB_CNT_BRS;
835 }
836
837 for (i = 0; i < cfd->len; i += sizeof(u32)) {
838 data = be32_to_cpup((__be32 *)&cfd->data[i]);
839 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
840 }
841
842 can_put_echo_skb(skb, dev, 0, 0);
843
844 priv->write(can_id, &priv->tx_mb->can_id);
845 priv->write(ctrl, &priv->tx_mb->can_ctrl);
846
847 /* Errata ERR005829 step8:
848 * Write twice INACTIVE(0x8) code to first MB.
849 */
850 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
851 &priv->tx_mb_reserved->can_ctrl);
852 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
853 &priv->tx_mb_reserved->can_ctrl);
854
855 return NETDEV_TX_OK;
856 }
857
flexcan_irq_bus_err(struct net_device * dev,u32 reg_esr)858 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
859 {
860 struct flexcan_priv *priv = netdev_priv(dev);
861 struct flexcan_regs __iomem *regs = priv->regs;
862 struct sk_buff *skb;
863 struct can_frame *cf;
864 bool rx_errors = false, tx_errors = false;
865 u32 timestamp;
866 int err;
867
868 timestamp = priv->read(®s->timer) << 16;
869
870 skb = alloc_can_err_skb(dev, &cf);
871 if (unlikely(!skb))
872 return;
873
874 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
875
876 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
877 netdev_dbg(dev, "BIT1_ERR irq\n");
878 cf->data[2] |= CAN_ERR_PROT_BIT1;
879 tx_errors = true;
880 }
881 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
882 netdev_dbg(dev, "BIT0_ERR irq\n");
883 cf->data[2] |= CAN_ERR_PROT_BIT0;
884 tx_errors = true;
885 }
886 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
887 netdev_dbg(dev, "ACK_ERR irq\n");
888 cf->can_id |= CAN_ERR_ACK;
889 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
890 tx_errors = true;
891 }
892 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
893 netdev_dbg(dev, "CRC_ERR irq\n");
894 cf->data[2] |= CAN_ERR_PROT_BIT;
895 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
896 rx_errors = true;
897 }
898 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
899 netdev_dbg(dev, "FRM_ERR irq\n");
900 cf->data[2] |= CAN_ERR_PROT_FORM;
901 rx_errors = true;
902 }
903 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
904 netdev_dbg(dev, "STF_ERR irq\n");
905 cf->data[2] |= CAN_ERR_PROT_STUFF;
906 rx_errors = true;
907 }
908
909 priv->can.can_stats.bus_error++;
910 if (rx_errors)
911 dev->stats.rx_errors++;
912 if (tx_errors)
913 dev->stats.tx_errors++;
914
915 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
916 if (err)
917 dev->stats.rx_fifo_errors++;
918 }
919
flexcan_irq_state(struct net_device * dev,u32 reg_esr)920 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
921 {
922 struct flexcan_priv *priv = netdev_priv(dev);
923 struct flexcan_regs __iomem *regs = priv->regs;
924 struct sk_buff *skb;
925 struct can_frame *cf;
926 enum can_state new_state, rx_state, tx_state;
927 int flt;
928 struct can_berr_counter bec;
929 u32 timestamp;
930 int err;
931
932 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
933 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
934 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
935 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
936 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
937 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
938 new_state = max(tx_state, rx_state);
939 } else {
940 __flexcan_get_berr_counter(dev, &bec);
941 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
942 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
943 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
944 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
945 }
946
947 /* state hasn't changed */
948 if (likely(new_state == priv->can.state))
949 return;
950
951 timestamp = priv->read(®s->timer) << 16;
952
953 skb = alloc_can_err_skb(dev, &cf);
954 if (unlikely(!skb))
955 return;
956
957 can_change_state(dev, cf, tx_state, rx_state);
958
959 if (unlikely(new_state == CAN_STATE_BUS_OFF))
960 can_bus_off(dev);
961
962 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
963 if (err)
964 dev->stats.rx_fifo_errors++;
965 }
966
flexcan_read64_mask(struct flexcan_priv * priv,void __iomem * addr,u64 mask)967 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
968 {
969 u64 reg = 0;
970
971 if (upper_32_bits(mask))
972 reg = (u64)priv->read(addr - 4) << 32;
973 if (lower_32_bits(mask))
974 reg |= priv->read(addr);
975
976 return reg & mask;
977 }
978
flexcan_write64(struct flexcan_priv * priv,u64 val,void __iomem * addr)979 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr)
980 {
981 if (upper_32_bits(val))
982 priv->write(upper_32_bits(val), addr - 4);
983 if (lower_32_bits(val))
984 priv->write(lower_32_bits(val), addr);
985 }
986
flexcan_read_reg_iflag_rx(struct flexcan_priv * priv)987 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
988 {
989 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
990 }
991
flexcan_read_reg_iflag_tx(struct flexcan_priv * priv)992 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv)
993 {
994 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask);
995 }
996
rx_offload_to_priv(struct can_rx_offload * offload)997 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
998 {
999 return container_of(offload, struct flexcan_priv, offload);
1000 }
1001
flexcan_mailbox_read(struct can_rx_offload * offload,unsigned int n,u32 * timestamp,bool drop)1002 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload,
1003 unsigned int n, u32 *timestamp,
1004 bool drop)
1005 {
1006 struct flexcan_priv *priv = rx_offload_to_priv(offload);
1007 struct flexcan_regs __iomem *regs = priv->regs;
1008 struct flexcan_mb __iomem *mb;
1009 struct sk_buff *skb;
1010 struct canfd_frame *cfd;
1011 u32 reg_ctrl, reg_id, reg_iflag1;
1012 int i;
1013
1014 if (unlikely(drop)) {
1015 skb = ERR_PTR(-ENOBUFS);
1016 goto mark_as_read;
1017 }
1018
1019 mb = flexcan_get_mb(priv, n);
1020
1021 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1022 u32 code;
1023
1024 do {
1025 reg_ctrl = priv->read(&mb->can_ctrl);
1026 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
1027
1028 /* is this MB empty? */
1029 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
1030 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
1031 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
1032 return NULL;
1033
1034 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
1035 /* This MB was overrun, we lost data */
1036 offload->dev->stats.rx_over_errors++;
1037 offload->dev->stats.rx_errors++;
1038 }
1039 } else {
1040 reg_iflag1 = priv->read(®s->iflag1);
1041 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
1042 return NULL;
1043
1044 reg_ctrl = priv->read(&mb->can_ctrl);
1045 }
1046
1047 if (reg_ctrl & FLEXCAN_MB_CNT_EDL)
1048 skb = alloc_canfd_skb(offload->dev, &cfd);
1049 else
1050 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd);
1051 if (unlikely(!skb)) {
1052 skb = ERR_PTR(-ENOMEM);
1053 goto mark_as_read;
1054 }
1055
1056 /* increase timstamp to full 32 bit */
1057 *timestamp = reg_ctrl << 16;
1058
1059 reg_id = priv->read(&mb->can_id);
1060 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
1061 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
1062 else
1063 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK;
1064
1065 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) {
1066 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf);
1067
1068 if (reg_ctrl & FLEXCAN_MB_CNT_BRS)
1069 cfd->flags |= CANFD_BRS;
1070 } else {
1071 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf);
1072
1073 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
1074 cfd->can_id |= CAN_RTR_FLAG;
1075 }
1076
1077 if (reg_ctrl & FLEXCAN_MB_CNT_ESI)
1078 cfd->flags |= CANFD_ESI;
1079
1080 for (i = 0; i < cfd->len; i += sizeof(u32)) {
1081 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
1082 *(__be32 *)(cfd->data + i) = data;
1083 }
1084
1085 mark_as_read:
1086 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1087 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1);
1088 else
1089 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
1090
1091 /* Read the Free Running Timer. It is optional but recommended
1092 * to unlock Mailbox as soon as possible and make it available
1093 * for reception.
1094 */
1095 priv->read(®s->timer);
1096
1097 return skb;
1098 }
1099
flexcan_irq(int irq,void * dev_id)1100 static irqreturn_t flexcan_irq(int irq, void *dev_id)
1101 {
1102 struct net_device *dev = dev_id;
1103 struct net_device_stats *stats = &dev->stats;
1104 struct flexcan_priv *priv = netdev_priv(dev);
1105 struct flexcan_regs __iomem *regs = priv->regs;
1106 irqreturn_t handled = IRQ_NONE;
1107 u64 reg_iflag_tx;
1108 u32 reg_esr;
1109 enum can_state last_state = priv->can.state;
1110
1111 /* reception interrupt */
1112 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1113 u64 reg_iflag_rx;
1114 int ret;
1115
1116 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) {
1117 handled = IRQ_HANDLED;
1118 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
1119 reg_iflag_rx);
1120 if (!ret)
1121 break;
1122 }
1123 } else {
1124 u32 reg_iflag1;
1125
1126 reg_iflag1 = priv->read(®s->iflag1);
1127 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
1128 handled = IRQ_HANDLED;
1129 can_rx_offload_irq_offload_fifo(&priv->offload);
1130 }
1131
1132 /* FIFO overflow interrupt */
1133 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
1134 handled = IRQ_HANDLED;
1135 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
1136 ®s->iflag1);
1137 dev->stats.rx_over_errors++;
1138 dev->stats.rx_errors++;
1139 }
1140 }
1141
1142 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv);
1143
1144 /* transmission complete interrupt */
1145 if (reg_iflag_tx & priv->tx_mask) {
1146 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
1147
1148 handled = IRQ_HANDLED;
1149 stats->tx_bytes +=
1150 can_rx_offload_get_echo_skb(&priv->offload, 0,
1151 reg_ctrl << 16, NULL);
1152 stats->tx_packets++;
1153 can_led_event(dev, CAN_LED_EVENT_TX);
1154
1155 /* after sending a RTR frame MB is in RX mode */
1156 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1157 &priv->tx_mb->can_ctrl);
1158 flexcan_write64(priv, priv->tx_mask, ®s->iflag1);
1159 netif_wake_queue(dev);
1160 }
1161
1162 reg_esr = priv->read(®s->esr);
1163
1164 /* ACK all bus error, state change and wake IRQ sources */
1165 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) {
1166 handled = IRQ_HANDLED;
1167 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr);
1168 }
1169
1170 /* state change interrupt or broken error state quirk fix is enabled */
1171 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
1172 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
1173 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
1174 flexcan_irq_state(dev, reg_esr);
1175
1176 /* bus error IRQ - handle if bus error reporting is activated */
1177 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
1178 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1179 flexcan_irq_bus_err(dev, reg_esr);
1180
1181 /* availability of error interrupt among state transitions in case
1182 * bus error reporting is de-activated and
1183 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
1184 * +--------------------------------------------------------------+
1185 * | +----------------------------------------------+ [stopped / |
1186 * | | | sleeping] -+
1187 * +-+-> active <-> warning <-> passive -> bus off -+
1188 * ___________^^^^^^^^^^^^_______________________________
1189 * disabled(1) enabled disabled
1190 *
1191 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
1192 */
1193 if ((last_state != priv->can.state) &&
1194 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
1195 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1196 switch (priv->can.state) {
1197 case CAN_STATE_ERROR_ACTIVE:
1198 if (priv->devtype_data->quirks &
1199 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
1200 flexcan_error_irq_enable(priv);
1201 else
1202 flexcan_error_irq_disable(priv);
1203 break;
1204
1205 case CAN_STATE_ERROR_WARNING:
1206 flexcan_error_irq_enable(priv);
1207 break;
1208
1209 case CAN_STATE_ERROR_PASSIVE:
1210 case CAN_STATE_BUS_OFF:
1211 flexcan_error_irq_disable(priv);
1212 break;
1213
1214 default:
1215 break;
1216 }
1217 }
1218
1219 if (handled)
1220 can_rx_offload_irq_finish(&priv->offload);
1221
1222 return handled;
1223 }
1224
flexcan_set_bittiming_ctrl(const struct net_device * dev)1225 static void flexcan_set_bittiming_ctrl(const struct net_device *dev)
1226 {
1227 const struct flexcan_priv *priv = netdev_priv(dev);
1228 const struct can_bittiming *bt = &priv->can.bittiming;
1229 struct flexcan_regs __iomem *regs = priv->regs;
1230 u32 reg;
1231
1232 reg = priv->read(®s->ctrl);
1233 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1234 FLEXCAN_CTRL_RJW(0x3) |
1235 FLEXCAN_CTRL_PSEG1(0x7) |
1236 FLEXCAN_CTRL_PSEG2(0x7) |
1237 FLEXCAN_CTRL_PROPSEG(0x7));
1238
1239 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1240 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1241 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1242 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1243 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1244
1245 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1246 priv->write(reg, ®s->ctrl);
1247
1248 /* print chip status */
1249 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1250 priv->read(®s->mcr), priv->read(®s->ctrl));
1251 }
1252
flexcan_set_bittiming_cbt(const struct net_device * dev)1253 static void flexcan_set_bittiming_cbt(const struct net_device *dev)
1254 {
1255 struct flexcan_priv *priv = netdev_priv(dev);
1256 struct can_bittiming *bt = &priv->can.bittiming;
1257 struct can_bittiming *dbt = &priv->can.data_bittiming;
1258 struct flexcan_regs __iomem *regs = priv->regs;
1259 u32 reg_cbt, reg_fdctrl;
1260
1261 /* CBT */
1262 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit
1263 * long. The can_calc_bittiming() tries to divide the tseg1
1264 * equally between phase_seg1 and prop_seg, which may not fit
1265 * in CBT register. Therefore, if phase_seg1 is more than
1266 * possible value, increase prop_seg and decrease phase_seg1.
1267 */
1268 if (bt->phase_seg1 > 0x20) {
1269 bt->prop_seg += (bt->phase_seg1 - 0x20);
1270 bt->phase_seg1 = 0x20;
1271 }
1272
1273 reg_cbt = FLEXCAN_CBT_BTF |
1274 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) |
1275 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) |
1276 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) |
1277 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) |
1278 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1);
1279
1280 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt);
1281 priv->write(reg_cbt, ®s->cbt);
1282
1283 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1284 u32 reg_fdcbt, reg_ctrl2;
1285
1286 if (bt->brp != dbt->brp)
1287 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n",
1288 dbt->brp, bt->brp);
1289
1290 /* FDCBT */
1291 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is
1292 * 5 bit long. The can_calc_bittiming tries to divide
1293 * the tseg1 equally between phase_seg1 and prop_seg,
1294 * which may not fit in FDCBT register. Therefore, if
1295 * phase_seg1 is more than possible value, increase
1296 * prop_seg and decrease phase_seg1
1297 */
1298 if (dbt->phase_seg1 > 0x8) {
1299 dbt->prop_seg += (dbt->phase_seg1 - 0x8);
1300 dbt->phase_seg1 = 0x8;
1301 }
1302
1303 reg_fdcbt = priv->read(®s->fdcbt);
1304 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) |
1305 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) |
1306 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) |
1307 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) |
1308 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7));
1309
1310 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) |
1311 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) |
1312 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) |
1313 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) |
1314 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1);
1315
1316 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt);
1317 priv->write(reg_fdcbt, ®s->fdcbt);
1318
1319 /* CTRL2 */
1320 reg_ctrl2 = priv->read(®s->ctrl2);
1321 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN;
1322 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
1323 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
1324
1325 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2);
1326 priv->write(reg_ctrl2, ®s->ctrl2);
1327 }
1328
1329 /* FDCTRL */
1330 reg_fdctrl = priv->read(®s->fdctrl);
1331 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE |
1332 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f));
1333
1334 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1335 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
1336
1337 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1338 /* TDC must be disabled for Loop Back mode */
1339 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
1340 } else {
1341 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN |
1342 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF,
1343 ((dbt->phase_seg1 - 1) +
1344 dbt->prop_seg + 2) *
1345 ((dbt->brp - 1 ) + 1));
1346 }
1347 }
1348
1349 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl);
1350 priv->write(reg_fdctrl, ®s->fdctrl);
1351
1352 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n",
1353 __func__,
1354 priv->read(®s->mcr), priv->read(®s->ctrl),
1355 priv->read(®s->ctrl2), priv->read(®s->fdctrl),
1356 priv->read(®s->cbt), priv->read(®s->fdcbt));
1357 }
1358
flexcan_set_bittiming(struct net_device * dev)1359 static void flexcan_set_bittiming(struct net_device *dev)
1360 {
1361 const struct flexcan_priv *priv = netdev_priv(dev);
1362 struct flexcan_regs __iomem *regs = priv->regs;
1363 u32 reg;
1364
1365 reg = priv->read(®s->ctrl);
1366 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP |
1367 FLEXCAN_CTRL_LOM);
1368
1369 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1370 reg |= FLEXCAN_CTRL_LPB;
1371 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1372 reg |= FLEXCAN_CTRL_LOM;
1373 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1374 reg |= FLEXCAN_CTRL_SMP;
1375
1376 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1377 priv->write(reg, ®s->ctrl);
1378
1379 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD)
1380 return flexcan_set_bittiming_cbt(dev);
1381 else
1382 return flexcan_set_bittiming_ctrl(dev);
1383 }
1384
flexcan_ram_init(struct net_device * dev)1385 static void flexcan_ram_init(struct net_device *dev)
1386 {
1387 struct flexcan_priv *priv = netdev_priv(dev);
1388 struct flexcan_regs __iomem *regs = priv->regs;
1389 u32 reg_ctrl2;
1390
1391 /* 11.8.3.13 Detection and correction of memory errors:
1392 * CTRL2[WRMFRZ] grants write access to all memory positions
1393 * that require initialization, ranging from 0x080 to 0xADF
1394 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled.
1395 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers
1396 * need to be initialized as well. MCR[RFEN] must not be set
1397 * during memory initialization.
1398 */
1399 reg_ctrl2 = priv->read(®s->ctrl2);
1400 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
1401 priv->write(reg_ctrl2, ®s->ctrl2);
1402
1403 memset_io(®s->mb[0][0], 0,
1404 offsetof(struct flexcan_regs, rx_smb1[3]) -
1405 offsetof(struct flexcan_regs, mb[0][0]) + 0x4);
1406
1407 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1408 memset_io(®s->tx_smb_fd[0], 0,
1409 offsetof(struct flexcan_regs, rx_smb1_fd[17]) -
1410 offsetof(struct flexcan_regs, tx_smb_fd[0]) + 0x4);
1411
1412 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ;
1413 priv->write(reg_ctrl2, ®s->ctrl2);
1414 }
1415
flexcan_rx_offload_setup(struct net_device * dev)1416 static int flexcan_rx_offload_setup(struct net_device *dev)
1417 {
1418 struct flexcan_priv *priv = netdev_priv(dev);
1419 int err;
1420
1421 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1422 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN;
1423 else
1424 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1425
1426 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_NR_MB_16)
1427 priv->mb_count = 16;
1428 else
1429 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1430 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1431
1432 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1433 priv->tx_mb_reserved =
1434 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1435 else
1436 priv->tx_mb_reserved =
1437 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1438 priv->tx_mb_idx = priv->mb_count - 1;
1439 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1440 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1441
1442 priv->offload.mailbox_read = flexcan_mailbox_read;
1443
1444 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1445 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1446 priv->offload.mb_last = priv->mb_count - 2;
1447
1448 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last,
1449 priv->offload.mb_first);
1450 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1451 } else {
1452 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1453 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1454 err = can_rx_offload_add_fifo(dev, &priv->offload,
1455 FLEXCAN_NAPI_WEIGHT);
1456 }
1457
1458 return err;
1459 }
1460
flexcan_chip_interrupts_enable(const struct net_device * dev)1461 static void flexcan_chip_interrupts_enable(const struct net_device *dev)
1462 {
1463 const struct flexcan_priv *priv = netdev_priv(dev);
1464 struct flexcan_regs __iomem *regs = priv->regs;
1465 u64 reg_imask;
1466
1467 disable_irq(dev->irq);
1468 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1469 reg_imask = priv->rx_mask | priv->tx_mask;
1470 priv->write(upper_32_bits(reg_imask), ®s->imask2);
1471 priv->write(lower_32_bits(reg_imask), ®s->imask1);
1472 enable_irq(dev->irq);
1473 }
1474
flexcan_chip_interrupts_disable(const struct net_device * dev)1475 static void flexcan_chip_interrupts_disable(const struct net_device *dev)
1476 {
1477 const struct flexcan_priv *priv = netdev_priv(dev);
1478 struct flexcan_regs __iomem *regs = priv->regs;
1479
1480 priv->write(0, ®s->imask2);
1481 priv->write(0, ®s->imask1);
1482 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1483 ®s->ctrl);
1484 }
1485
1486 /* flexcan_chip_start
1487 *
1488 * this functions is entered with clocks enabled
1489 *
1490 */
flexcan_chip_start(struct net_device * dev)1491 static int flexcan_chip_start(struct net_device *dev)
1492 {
1493 struct flexcan_priv *priv = netdev_priv(dev);
1494 struct flexcan_regs __iomem *regs = priv->regs;
1495 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1496 int err, i;
1497 struct flexcan_mb __iomem *mb;
1498
1499 /* enable module */
1500 err = flexcan_chip_enable(priv);
1501 if (err)
1502 return err;
1503
1504 /* soft reset */
1505 err = flexcan_chip_softreset(priv);
1506 if (err)
1507 goto out_chip_disable;
1508
1509 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC)
1510 flexcan_ram_init(dev);
1511
1512 flexcan_set_bittiming(dev);
1513
1514 /* set freeze, halt */
1515 err = flexcan_chip_freeze(priv);
1516 if (err)
1517 goto out_chip_disable;
1518
1519 /* MCR
1520 *
1521 * only supervisor access
1522 * enable warning int
1523 * enable individual RX masking
1524 * choose format C
1525 * set max mailbox number
1526 */
1527 reg_mcr = priv->read(®s->mcr);
1528 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1529 reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ |
1530 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1531
1532 /* MCR
1533 *
1534 * FIFO:
1535 * - disable for timestamp mode
1536 * - enable for FIFO mode
1537 */
1538 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1539 reg_mcr &= ~FLEXCAN_MCR_FEN;
1540 else
1541 reg_mcr |= FLEXCAN_MCR_FEN;
1542
1543 /* MCR
1544 *
1545 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1546 * asserted because this will impede the self reception
1547 * of a transmitted message. This is not documented in
1548 * earlier versions of flexcan block guide.
1549 *
1550 * Self Reception:
1551 * - enable Self Reception for loopback mode
1552 * (by clearing "Self Reception Disable" bit)
1553 * - disable for normal operation
1554 */
1555 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1556 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1557 else
1558 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1559
1560 /* MCR - CAN-FD */
1561 if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
1562 reg_mcr |= FLEXCAN_MCR_FDEN;
1563 else
1564 reg_mcr &= ~FLEXCAN_MCR_FDEN;
1565
1566 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1567 priv->write(reg_mcr, ®s->mcr);
1568
1569 /* CTRL
1570 *
1571 * disable timer sync feature
1572 *
1573 * disable auto busoff recovery
1574 * transmit lowest buffer first
1575 *
1576 * enable tx and rx warning interrupt
1577 * enable bus off interrupt
1578 * (== FLEXCAN_CTRL_ERR_STATE)
1579 */
1580 reg_ctrl = priv->read(®s->ctrl);
1581 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1582 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1583 FLEXCAN_CTRL_ERR_STATE;
1584
1585 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1586 * on most Flexcan cores, too. Otherwise we don't get
1587 * any error warning or passive interrupts.
1588 */
1589 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1590 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1591 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1592 else
1593 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1594
1595 /* save for later use */
1596 priv->reg_ctrl_default = reg_ctrl;
1597 /* leave interrupts disabled for now */
1598 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1599 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1600 priv->write(reg_ctrl, ®s->ctrl);
1601
1602 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1603 reg_ctrl2 = priv->read(®s->ctrl2);
1604 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1605 priv->write(reg_ctrl2, ®s->ctrl2);
1606 }
1607
1608 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
1609 u32 reg_fdctrl;
1610
1611 reg_fdctrl = priv->read(®s->fdctrl);
1612 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) |
1613 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3));
1614
1615 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1616 reg_fdctrl |=
1617 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1618 FLEXCAN_FDCTRL_MBDSR_64) |
1619 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1620 FLEXCAN_FDCTRL_MBDSR_64);
1621 } else {
1622 reg_fdctrl |=
1623 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1,
1624 FLEXCAN_FDCTRL_MBDSR_8) |
1625 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0,
1626 FLEXCAN_FDCTRL_MBDSR_8);
1627 }
1628
1629 netdev_dbg(dev, "%s: writing fdctrl=0x%08x",
1630 __func__, reg_fdctrl);
1631 priv->write(reg_fdctrl, ®s->fdctrl);
1632 }
1633
1634 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1635 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1636 mb = flexcan_get_mb(priv, i);
1637 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1638 &mb->can_ctrl);
1639 }
1640 } else {
1641 /* clear and invalidate unused mailboxes first */
1642 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1643 mb = flexcan_get_mb(priv, i);
1644 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1645 &mb->can_ctrl);
1646 }
1647 }
1648
1649 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1650 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1651 &priv->tx_mb_reserved->can_ctrl);
1652
1653 /* mark TX mailbox as INACTIVE */
1654 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1655 &priv->tx_mb->can_ctrl);
1656
1657 /* acceptance mask/acceptance code (accept everything) */
1658 priv->write(0x0, ®s->rxgmask);
1659 priv->write(0x0, ®s->rx14mask);
1660 priv->write(0x0, ®s->rx15mask);
1661
1662 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1663 priv->write(0x0, ®s->rxfgmask);
1664
1665 /* clear acceptance filters */
1666 for (i = 0; i < priv->mb_count; i++)
1667 priv->write(0, ®s->rximr[i]);
1668
1669 /* On Vybrid, disable non-correctable errors interrupt and
1670 * freeze mode. It still can correct the correctable errors
1671 * when HW supports ECC.
1672 *
1673 * This also works around errata e5295 which generates false
1674 * positive memory errors and put the device in freeze mode.
1675 */
1676 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1677 /* Follow the protocol as described in "Detection
1678 * and Correction of Memory Errors" to write to
1679 * MECR register (step 1 - 5)
1680 *
1681 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1
1682 * 2. set CTRL2[ECRWRE]
1683 */
1684 reg_ctrl2 = priv->read(®s->ctrl2);
1685 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1686 priv->write(reg_ctrl2, ®s->ctrl2);
1687
1688 /* 3. clear MECR[ECRWRDIS] */
1689 reg_mecr = priv->read(®s->mecr);
1690 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1691 priv->write(reg_mecr, ®s->mecr);
1692
1693 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */
1694 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1695 FLEXCAN_MECR_FANCEI_MSK);
1696 priv->write(reg_mecr, ®s->mecr);
1697
1698 /* 5. after configuration done, lock MECR by either
1699 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE]
1700 */
1701 reg_mecr |= FLEXCAN_MECR_ECRWRDIS;
1702 priv->write(reg_mecr, ®s->mecr);
1703
1704 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE;
1705 priv->write(reg_ctrl2, ®s->ctrl2);
1706 }
1707
1708 /* synchronize with the can bus */
1709 err = flexcan_chip_unfreeze(priv);
1710 if (err)
1711 goto out_chip_disable;
1712
1713 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1714
1715 /* print chip status */
1716 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1717 priv->read(®s->mcr), priv->read(®s->ctrl));
1718
1719 return 0;
1720
1721 out_chip_disable:
1722 flexcan_chip_disable(priv);
1723 return err;
1724 }
1725
1726 /* __flexcan_chip_stop
1727 *
1728 * this function is entered with clocks enabled
1729 */
__flexcan_chip_stop(struct net_device * dev,bool disable_on_error)1730 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1731 {
1732 struct flexcan_priv *priv = netdev_priv(dev);
1733 int err;
1734
1735 /* freeze + disable module */
1736 err = flexcan_chip_freeze(priv);
1737 if (err && !disable_on_error)
1738 return err;
1739 err = flexcan_chip_disable(priv);
1740 if (err && !disable_on_error)
1741 goto out_chip_unfreeze;
1742
1743 priv->can.state = CAN_STATE_STOPPED;
1744
1745 return 0;
1746
1747 out_chip_unfreeze:
1748 flexcan_chip_unfreeze(priv);
1749
1750 return err;
1751 }
1752
flexcan_chip_stop_disable_on_error(struct net_device * dev)1753 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1754 {
1755 return __flexcan_chip_stop(dev, true);
1756 }
1757
flexcan_chip_stop(struct net_device * dev)1758 static inline int flexcan_chip_stop(struct net_device *dev)
1759 {
1760 return __flexcan_chip_stop(dev, false);
1761 }
1762
flexcan_open(struct net_device * dev)1763 static int flexcan_open(struct net_device *dev)
1764 {
1765 struct flexcan_priv *priv = netdev_priv(dev);
1766 int err;
1767
1768 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) &&
1769 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) {
1770 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n");
1771 return -EINVAL;
1772 }
1773
1774 err = pm_runtime_get_sync(priv->dev);
1775 if (err < 0) {
1776 pm_runtime_put_noidle(priv->dev);
1777 return err;
1778 }
1779
1780 err = open_candev(dev);
1781 if (err)
1782 goto out_runtime_put;
1783
1784 err = flexcan_transceiver_enable(priv);
1785 if (err)
1786 goto out_close;
1787
1788 err = flexcan_rx_offload_setup(dev);
1789 if (err)
1790 goto out_transceiver_disable;
1791
1792 err = flexcan_chip_start(dev);
1793 if (err)
1794 goto out_can_rx_offload_del;
1795
1796 can_rx_offload_enable(&priv->offload);
1797
1798 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1799 if (err)
1800 goto out_can_rx_offload_disable;
1801
1802 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1803 err = request_irq(priv->irq_boff,
1804 flexcan_irq, IRQF_SHARED, dev->name, dev);
1805 if (err)
1806 goto out_free_irq;
1807
1808 err = request_irq(priv->irq_err,
1809 flexcan_irq, IRQF_SHARED, dev->name, dev);
1810 if (err)
1811 goto out_free_irq_boff;
1812 }
1813
1814 flexcan_chip_interrupts_enable(dev);
1815
1816 can_led_event(dev, CAN_LED_EVENT_OPEN);
1817
1818 netif_start_queue(dev);
1819
1820 return 0;
1821
1822 out_free_irq_boff:
1823 free_irq(priv->irq_boff, dev);
1824 out_free_irq:
1825 free_irq(dev->irq, dev);
1826 out_can_rx_offload_disable:
1827 can_rx_offload_disable(&priv->offload);
1828 flexcan_chip_stop(dev);
1829 out_can_rx_offload_del:
1830 can_rx_offload_del(&priv->offload);
1831 out_transceiver_disable:
1832 flexcan_transceiver_disable(priv);
1833 out_close:
1834 close_candev(dev);
1835 out_runtime_put:
1836 pm_runtime_put(priv->dev);
1837
1838 return err;
1839 }
1840
flexcan_close(struct net_device * dev)1841 static int flexcan_close(struct net_device *dev)
1842 {
1843 struct flexcan_priv *priv = netdev_priv(dev);
1844
1845 netif_stop_queue(dev);
1846 flexcan_chip_interrupts_disable(dev);
1847
1848 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
1849 free_irq(priv->irq_err, dev);
1850 free_irq(priv->irq_boff, dev);
1851 }
1852
1853 free_irq(dev->irq, dev);
1854 can_rx_offload_disable(&priv->offload);
1855 flexcan_chip_stop_disable_on_error(dev);
1856
1857 can_rx_offload_del(&priv->offload);
1858 flexcan_transceiver_disable(priv);
1859 close_candev(dev);
1860
1861 pm_runtime_put(priv->dev);
1862
1863 can_led_event(dev, CAN_LED_EVENT_STOP);
1864
1865 return 0;
1866 }
1867
flexcan_set_mode(struct net_device * dev,enum can_mode mode)1868 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1869 {
1870 int err;
1871
1872 switch (mode) {
1873 case CAN_MODE_START:
1874 err = flexcan_chip_start(dev);
1875 if (err)
1876 return err;
1877
1878 flexcan_chip_interrupts_enable(dev);
1879
1880 netif_wake_queue(dev);
1881 break;
1882
1883 default:
1884 return -EOPNOTSUPP;
1885 }
1886
1887 return 0;
1888 }
1889
1890 static const struct net_device_ops flexcan_netdev_ops = {
1891 .ndo_open = flexcan_open,
1892 .ndo_stop = flexcan_close,
1893 .ndo_start_xmit = flexcan_start_xmit,
1894 .ndo_change_mtu = can_change_mtu,
1895 };
1896
register_flexcandev(struct net_device * dev)1897 static int register_flexcandev(struct net_device *dev)
1898 {
1899 struct flexcan_priv *priv = netdev_priv(dev);
1900 struct flexcan_regs __iomem *regs = priv->regs;
1901 u32 reg, err;
1902
1903 err = flexcan_clks_enable(priv);
1904 if (err)
1905 return err;
1906
1907 /* select "bus clock", chip must be disabled */
1908 err = flexcan_chip_disable(priv);
1909 if (err)
1910 goto out_clks_disable;
1911
1912 reg = priv->read(®s->ctrl);
1913 if (priv->clk_src)
1914 reg |= FLEXCAN_CTRL_CLK_SRC;
1915 else
1916 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1917 priv->write(reg, ®s->ctrl);
1918
1919 err = flexcan_chip_enable(priv);
1920 if (err)
1921 goto out_chip_disable;
1922
1923 /* set freeze, halt */
1924 err = flexcan_chip_freeze(priv);
1925 if (err)
1926 goto out_chip_disable;
1927
1928 /* activate FIFO, restrict register access */
1929 reg = priv->read(®s->mcr);
1930 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1931 priv->write(reg, ®s->mcr);
1932
1933 /* Currently we only support newer versions of this core
1934 * featuring a RX hardware FIFO (although this driver doesn't
1935 * make use of it on some cores). Older cores, found on some
1936 * Coldfire derivates are not tested.
1937 */
1938 reg = priv->read(®s->mcr);
1939 if (!(reg & FLEXCAN_MCR_FEN)) {
1940 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1941 err = -ENODEV;
1942 goto out_chip_disable;
1943 }
1944
1945 err = register_candev(dev);
1946 if (err)
1947 goto out_chip_disable;
1948
1949 /* Disable core and let pm_runtime_put() disable the clocks.
1950 * If CONFIG_PM is not enabled, the clocks will stay powered.
1951 */
1952 flexcan_chip_disable(priv);
1953 pm_runtime_put(priv->dev);
1954
1955 return 0;
1956
1957 out_chip_disable:
1958 flexcan_chip_disable(priv);
1959 out_clks_disable:
1960 flexcan_clks_disable(priv);
1961 return err;
1962 }
1963
unregister_flexcandev(struct net_device * dev)1964 static void unregister_flexcandev(struct net_device *dev)
1965 {
1966 unregister_candev(dev);
1967 }
1968
flexcan_setup_stop_mode_gpr(struct platform_device * pdev)1969 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
1970 {
1971 struct net_device *dev = platform_get_drvdata(pdev);
1972 struct device_node *np = pdev->dev.of_node;
1973 struct device_node *gpr_np;
1974 struct flexcan_priv *priv;
1975 phandle phandle;
1976 u32 out_val[3];
1977 int ret;
1978
1979 if (!np)
1980 return -EINVAL;
1981
1982 /* stop mode property format is:
1983 * <&gpr req_gpr req_bit>.
1984 */
1985 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1986 ARRAY_SIZE(out_val));
1987 if (ret) {
1988 dev_dbg(&pdev->dev, "no stop-mode property\n");
1989 return ret;
1990 }
1991 phandle = *out_val;
1992
1993 gpr_np = of_find_node_by_phandle(phandle);
1994 if (!gpr_np) {
1995 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1996 return -ENODEV;
1997 }
1998
1999 priv = netdev_priv(dev);
2000 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
2001 if (IS_ERR(priv->stm.gpr)) {
2002 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
2003 ret = PTR_ERR(priv->stm.gpr);
2004 goto out_put_node;
2005 }
2006
2007 priv->stm.req_gpr = out_val[1];
2008 priv->stm.req_bit = out_val[2];
2009
2010 dev_dbg(&pdev->dev,
2011 "gpr %s req_gpr=0x02%x req_bit=%u\n",
2012 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit);
2013
2014 return 0;
2015
2016 out_put_node:
2017 of_node_put(gpr_np);
2018 return ret;
2019 }
2020
flexcan_setup_stop_mode_scfw(struct platform_device * pdev)2021 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev)
2022 {
2023 struct net_device *dev = platform_get_drvdata(pdev);
2024 struct flexcan_priv *priv;
2025 u8 scu_idx;
2026 int ret;
2027
2028 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx);
2029 if (ret < 0) {
2030 dev_dbg(&pdev->dev, "failed to get scu index\n");
2031 return ret;
2032 }
2033
2034 priv = netdev_priv(dev);
2035 priv->scu_idx = scu_idx;
2036
2037 /* this function could be deferred probe, return -EPROBE_DEFER */
2038 return imx_scu_get_handle(&priv->sc_ipc_handle);
2039 }
2040
2041 /* flexcan_setup_stop_mode - Setup stop mode for wakeup
2042 *
2043 * Return: = 0 setup stop mode successfully or doesn't support this feature
2044 * < 0 fail to setup stop mode (could be deferred probe)
2045 */
flexcan_setup_stop_mode(struct platform_device * pdev)2046 static int flexcan_setup_stop_mode(struct platform_device *pdev)
2047 {
2048 struct net_device *dev = platform_get_drvdata(pdev);
2049 struct flexcan_priv *priv;
2050 int ret;
2051
2052 priv = netdev_priv(dev);
2053
2054 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW)
2055 ret = flexcan_setup_stop_mode_scfw(pdev);
2056 else if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR)
2057 ret = flexcan_setup_stop_mode_gpr(pdev);
2058 else
2059 /* return 0 directly if doesn't support stop mode feature */
2060 return 0;
2061
2062 if (ret)
2063 return ret;
2064
2065 device_set_wakeup_capable(&pdev->dev, true);
2066
2067 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source"))
2068 device_set_wakeup_enable(&pdev->dev, true);
2069
2070 return 0;
2071 }
2072
2073 static const struct of_device_id flexcan_of_match[] = {
2074 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
2075 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
2076 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
2077 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
2078 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
2079 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
2080 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
2081 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
2082 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
2083 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
2084 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
2085 { /* sentinel */ },
2086 };
2087 MODULE_DEVICE_TABLE(of, flexcan_of_match);
2088
2089 static const struct platform_device_id flexcan_id_table[] = {
2090 {
2091 .name = "flexcan-mcf5441x",
2092 .driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data,
2093 }, {
2094 /* sentinel */
2095 },
2096 };
2097 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
2098
flexcan_probe(struct platform_device * pdev)2099 static int flexcan_probe(struct platform_device *pdev)
2100 {
2101 const struct of_device_id *of_id;
2102 const struct flexcan_devtype_data *devtype_data;
2103 struct net_device *dev;
2104 struct flexcan_priv *priv;
2105 struct regulator *reg_xceiver;
2106 struct clk *clk_ipg = NULL, *clk_per = NULL;
2107 struct flexcan_regs __iomem *regs;
2108 struct flexcan_platform_data *pdata;
2109 int err, irq;
2110 u8 clk_src = 1;
2111 u32 clock_freq = 0;
2112
2113 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver");
2114 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
2115 return -EPROBE_DEFER;
2116 else if (PTR_ERR(reg_xceiver) == -ENODEV)
2117 reg_xceiver = NULL;
2118 else if (IS_ERR(reg_xceiver))
2119 return PTR_ERR(reg_xceiver);
2120
2121 if (pdev->dev.of_node) {
2122 of_property_read_u32(pdev->dev.of_node,
2123 "clock-frequency", &clock_freq);
2124 of_property_read_u8(pdev->dev.of_node,
2125 "fsl,clk-source", &clk_src);
2126 } else {
2127 pdata = dev_get_platdata(&pdev->dev);
2128 if (pdata) {
2129 clock_freq = pdata->clock_frequency;
2130 clk_src = pdata->clk_src;
2131 }
2132 }
2133
2134 if (!clock_freq) {
2135 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2136 if (IS_ERR(clk_ipg)) {
2137 dev_err(&pdev->dev, "no ipg clock defined\n");
2138 return PTR_ERR(clk_ipg);
2139 }
2140
2141 clk_per = devm_clk_get(&pdev->dev, "per");
2142 if (IS_ERR(clk_per)) {
2143 dev_err(&pdev->dev, "no per clock defined\n");
2144 return PTR_ERR(clk_per);
2145 }
2146 clock_freq = clk_get_rate(clk_per);
2147 }
2148
2149 irq = platform_get_irq(pdev, 0);
2150 if (irq <= 0)
2151 return -ENODEV;
2152
2153 regs = devm_platform_ioremap_resource(pdev, 0);
2154 if (IS_ERR(regs))
2155 return PTR_ERR(regs);
2156
2157 of_id = of_match_device(flexcan_of_match, &pdev->dev);
2158 if (of_id)
2159 devtype_data = of_id->data;
2160 else if (platform_get_device_id(pdev)->driver_data)
2161 devtype_data = (struct flexcan_devtype_data *)
2162 platform_get_device_id(pdev)->driver_data;
2163 else
2164 return -ENODEV;
2165
2166 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
2167 !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) {
2168 dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
2169 return -EINVAL;
2170 }
2171
2172 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
2173 if (!dev)
2174 return -ENOMEM;
2175
2176 platform_set_drvdata(pdev, dev);
2177 SET_NETDEV_DEV(dev, &pdev->dev);
2178
2179 dev->netdev_ops = &flexcan_netdev_ops;
2180 dev->irq = irq;
2181 dev->flags |= IFF_ECHO;
2182
2183 priv = netdev_priv(dev);
2184
2185 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
2186 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
2187 priv->read = flexcan_read_be;
2188 priv->write = flexcan_write_be;
2189 } else {
2190 priv->read = flexcan_read_le;
2191 priv->write = flexcan_write_le;
2192 }
2193
2194 priv->dev = &pdev->dev;
2195 priv->can.clock.freq = clock_freq;
2196 priv->can.do_set_mode = flexcan_set_mode;
2197 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
2198 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2199 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
2200 CAN_CTRLMODE_BERR_REPORTING;
2201 priv->regs = regs;
2202 priv->clk_ipg = clk_ipg;
2203 priv->clk_per = clk_per;
2204 priv->clk_src = clk_src;
2205 priv->devtype_data = devtype_data;
2206 priv->reg_xceiver = reg_xceiver;
2207
2208 if (devtype_data->quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
2209 priv->irq_boff = platform_get_irq(pdev, 1);
2210 if (priv->irq_boff <= 0) {
2211 err = -ENODEV;
2212 goto failed_platform_get_irq;
2213 }
2214 priv->irq_err = platform_get_irq(pdev, 2);
2215 if (priv->irq_err <= 0) {
2216 err = -ENODEV;
2217 goto failed_platform_get_irq;
2218 }
2219 }
2220
2221 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) {
2222 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
2223 CAN_CTRLMODE_FD_NON_ISO;
2224 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
2225 priv->can.data_bittiming_const =
2226 &flexcan_fd_data_bittiming_const;
2227 } else {
2228 priv->can.bittiming_const = &flexcan_bittiming_const;
2229 }
2230
2231 pm_runtime_get_noresume(&pdev->dev);
2232 pm_runtime_set_active(&pdev->dev);
2233 pm_runtime_enable(&pdev->dev);
2234
2235 err = register_flexcandev(dev);
2236 if (err) {
2237 dev_err(&pdev->dev, "registering netdev failed\n");
2238 goto failed_register;
2239 }
2240
2241 err = flexcan_setup_stop_mode(pdev);
2242 if (err < 0) {
2243 if (err != -EPROBE_DEFER)
2244 dev_err(&pdev->dev, "setup stop mode failed\n");
2245 goto failed_setup_stop_mode;
2246 }
2247
2248 of_can_transceiver(dev);
2249 devm_can_led_init(dev);
2250
2251 return 0;
2252
2253 failed_setup_stop_mode:
2254 unregister_flexcandev(dev);
2255 failed_register:
2256 pm_runtime_put_noidle(&pdev->dev);
2257 pm_runtime_disable(&pdev->dev);
2258 failed_platform_get_irq:
2259 free_candev(dev);
2260 return err;
2261 }
2262
flexcan_remove(struct platform_device * pdev)2263 static int flexcan_remove(struct platform_device *pdev)
2264 {
2265 struct net_device *dev = platform_get_drvdata(pdev);
2266
2267 device_set_wakeup_enable(&pdev->dev, false);
2268 device_set_wakeup_capable(&pdev->dev, false);
2269 unregister_flexcandev(dev);
2270 pm_runtime_disable(&pdev->dev);
2271 free_candev(dev);
2272
2273 return 0;
2274 }
2275
flexcan_suspend(struct device * device)2276 static int __maybe_unused flexcan_suspend(struct device *device)
2277 {
2278 struct net_device *dev = dev_get_drvdata(device);
2279 struct flexcan_priv *priv = netdev_priv(dev);
2280 int err;
2281
2282 if (netif_running(dev)) {
2283 /* if wakeup is enabled, enter stop mode
2284 * else enter disabled mode.
2285 */
2286 if (device_may_wakeup(device)) {
2287 enable_irq_wake(dev->irq);
2288 err = flexcan_enter_stop_mode(priv);
2289 if (err)
2290 return err;
2291 } else {
2292 err = flexcan_chip_stop(dev);
2293 if (err)
2294 return err;
2295
2296 flexcan_chip_interrupts_disable(dev);
2297
2298 err = pinctrl_pm_select_sleep_state(device);
2299 if (err)
2300 return err;
2301 }
2302 netif_stop_queue(dev);
2303 netif_device_detach(dev);
2304 }
2305 priv->can.state = CAN_STATE_SLEEPING;
2306
2307 return 0;
2308 }
2309
flexcan_resume(struct device * device)2310 static int __maybe_unused flexcan_resume(struct device *device)
2311 {
2312 struct net_device *dev = dev_get_drvdata(device);
2313 struct flexcan_priv *priv = netdev_priv(dev);
2314 int err;
2315
2316 priv->can.state = CAN_STATE_ERROR_ACTIVE;
2317 if (netif_running(dev)) {
2318 netif_device_attach(dev);
2319 netif_start_queue(dev);
2320 if (device_may_wakeup(device)) {
2321 disable_irq_wake(dev->irq);
2322 err = flexcan_exit_stop_mode(priv);
2323 if (err)
2324 return err;
2325 } else {
2326 err = pinctrl_pm_select_default_state(device);
2327 if (err)
2328 return err;
2329
2330 err = flexcan_chip_start(dev);
2331 if (err)
2332 return err;
2333
2334 flexcan_chip_interrupts_enable(dev);
2335 }
2336 }
2337
2338 return 0;
2339 }
2340
flexcan_runtime_suspend(struct device * device)2341 static int __maybe_unused flexcan_runtime_suspend(struct device *device)
2342 {
2343 struct net_device *dev = dev_get_drvdata(device);
2344 struct flexcan_priv *priv = netdev_priv(dev);
2345
2346 flexcan_clks_disable(priv);
2347
2348 return 0;
2349 }
2350
flexcan_runtime_resume(struct device * device)2351 static int __maybe_unused flexcan_runtime_resume(struct device *device)
2352 {
2353 struct net_device *dev = dev_get_drvdata(device);
2354 struct flexcan_priv *priv = netdev_priv(dev);
2355
2356 return flexcan_clks_enable(priv);
2357 }
2358
flexcan_noirq_suspend(struct device * device)2359 static int __maybe_unused flexcan_noirq_suspend(struct device *device)
2360 {
2361 struct net_device *dev = dev_get_drvdata(device);
2362 struct flexcan_priv *priv = netdev_priv(dev);
2363
2364 if (netif_running(dev)) {
2365 int err;
2366
2367 if (device_may_wakeup(device))
2368 flexcan_enable_wakeup_irq(priv, true);
2369
2370 err = pm_runtime_force_suspend(device);
2371 if (err)
2372 return err;
2373 }
2374
2375 return 0;
2376 }
2377
flexcan_noirq_resume(struct device * device)2378 static int __maybe_unused flexcan_noirq_resume(struct device *device)
2379 {
2380 struct net_device *dev = dev_get_drvdata(device);
2381 struct flexcan_priv *priv = netdev_priv(dev);
2382
2383 if (netif_running(dev)) {
2384 int err;
2385
2386 err = pm_runtime_force_resume(device);
2387 if (err)
2388 return err;
2389
2390 if (device_may_wakeup(device))
2391 flexcan_enable_wakeup_irq(priv, false);
2392 }
2393
2394 return 0;
2395 }
2396
2397 static const struct dev_pm_ops flexcan_pm_ops = {
2398 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
2399 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
2400 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
2401 };
2402
2403 static struct platform_driver flexcan_driver = {
2404 .driver = {
2405 .name = DRV_NAME,
2406 .pm = &flexcan_pm_ops,
2407 .of_match_table = flexcan_of_match,
2408 },
2409 .probe = flexcan_probe,
2410 .remove = flexcan_remove,
2411 .id_table = flexcan_id_table,
2412 };
2413
2414 module_platform_driver(flexcan_driver);
2415
2416 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
2417 "Marc Kleine-Budde <kernel@pengutronix.de>");
2418 MODULE_LICENSE("GPL v2");
2419 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
2420
