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Searched refs:train_set (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/display/
Dg4x_dp.c822 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
824 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
827 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
850 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
869 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
884 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
908 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
910 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_set_signal_levels()
912 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_set_signal_levels()
935 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_set_signal_levels()
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Dintel_dp_link_training.c332 intel_dp->train_set[lane] = v | p; in intel_dp_get_adjust_train()
350 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
358 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train()
402 u8 train_set = intel_dp->train_set[0]; in intel_dp_set_signal_levels() local
406 train_set & DP_TRAIN_VOLTAGE_SWING_MASK, in intel_dp_set_signal_levels()
407 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", in intel_dp_set_signal_levels()
408 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> in intel_dp_set_signal_levels()
410 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? in intel_dp_set_signal_levels()
424 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_reset_link_train()
442 intel_dp->train_set, crtc_state->lane_count); in intel_dp_update_link_train()
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Dintel_display_types.h1575 u8 train_set[4]; member
Dintel_ddi.c1376 u8 train_set = intel_dp->train_set[0]; in intel_ddi_dp_level() local
1377 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
Dintel_display_debugfs.c1563 intel_dp->train_set[0]); in i915_displayport_test_data_show()
Dintel_dp.c3341 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Datombios_dp.c204 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
236 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
495 u8 train_set[4]; member
507 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
511 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
605 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
629 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
637 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
646 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
650 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
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/Linux-v5.15/drivers/gpu/drm/radeon/
Datombios_dp.c259 u8 train_set[4]) in dp_get_adjust_train()
291 train_set[lane] = v | p; in dp_get_adjust_train()
546 u8 train_set[4]; member
558 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
562 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
673 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
697 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
705 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
714 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
717 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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/Linux-v5.15/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c320 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
614 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
636 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
654 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
662 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
720 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
725 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
733 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in zynqmp_dp_link_train_cr()
863 memset(dp->train_set, 0, sizeof(dp->train_set)); in zynqmp_dp_train()
/Linux-v5.15/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c271 uint8_t train_set[4]; member
1302 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1391 intel_dp->train_set, in cdv_intel_dplink_set_level()
1396 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1496 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1507 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1514 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1535 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1541 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in cdv_intel_dp_start_link_train()
1547 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
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