Searched refs:ss_ctrl (Results 1 – 5 of 5) sorted by relevance
365 u32 ss_ctrl; in mxic_spi_mem_exec_op() local386 ss_ctrl = OP_CMD_BYTES(op->cmd.nbytes) | in mxic_spi_mem_exec_op()391 ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) | in mxic_spi_mem_exec_op()396 ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes); in mxic_spi_mem_exec_op()399 ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) | in mxic_spi_mem_exec_op()402 ss_ctrl |= OP_READ; in mxic_spi_mem_exec_op()404 ss_ctrl |= OP_DQS_EN; in mxic_spi_mem_exec_op()408 writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select)); in mxic_spi_mem_exec_op()
88 CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); in etm4_cfg_map_reg_offset()
245 config->ss_ctrl[i] = 0x0; in reset_store()1767 val = config->ss_ctrl[config->ss_idx]; in sshot_ctrl_show()1786 config->ss_ctrl[idx] = val & GENMASK(24, 0); in sshot_ctrl_store()
405 if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) in etm4_enable_hw()407 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); in etm4_enable_hw()
790 u32 ss_ctrl[ETM_MAX_SS_CMP]; member
