| /Linux-v5.15/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_vcn.h | 81 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ argument
87 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
91 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ argument
99 (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
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| D | vcn_v1_0.c | 631 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) in vcn_v1_0_clock_gating_dpg_mode() argument
642 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
644 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
673 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
676 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
679 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
682 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
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| D | vcn_v2_0.c | 589 uint8_t sram_sel, uint8_t indirect) in vcn_v2_0_clock_gating_dpg_mode() argument
621 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
625 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
629 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
633 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
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| D | vcn_v2_5.c | 657 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v2_5_clock_gating_dpg_mode() argument
689 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
693 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
697 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
701 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
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| D | vcn_v3_0.c | 841 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v3_0_clock_gating_dpg_mode() argument
873 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
877 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
881 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
885 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
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