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Searched refs:spx5_wr (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/drivers/net/ethernet/microchip/sparx5/
Dsparx5_vlan.c18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
152 spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); in sparx5_update_fwd()
153 spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); in sparx5_update_fwd()
154 spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); in sparx5_update_fwd()
164 spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port)); in sparx5_update_fwd()
165 spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); in sparx5_update_fwd()
166 spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); in sparx5_update_fwd()
168 spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port)); in sparx5_update_fwd()
[all …]
Dsparx5_fdma.c116 spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
118 spx5_wr(((u64)rx->dma) >> 32, sparx5, FDMA_DCB_LLP1(rx->channel_id)); in sparx5_fdma_rx_activate()
121 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_RX_DCB_MAX_DBS) | in sparx5_fdma_rx_activate()
141 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_activate()
162 spx5_wr(((u64)tx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_tx_activate()
164 spx5_wr(((u64)tx->dma) >> 32, sparx5, FDMA_DCB_LLP1(tx->channel_id)); in sparx5_fdma_tx_activate()
167 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_TX_DCB_MAX_DBS) | in sparx5_fdma_tx_activate()
177 spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_activate()
190 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_rx_reload()
196 spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_tx_reload()
[all …]
Dsparx5_packet.c26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
170 spx5_wr(QS_INJ_CTRL_SOF_SET(1) | in sparx5_inject()
176 spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp)); in sparx5_inject()
183 spx5_wr(val, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
188 spx5_wr(0, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
193 spx5_wr(QS_INJ_CTRL_GAP_SIZE_SET(1) | in sparx5_inject()
199 spx5_wr(0, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
265 spx5_wr(QS_XTR_GRP_CFG_MODE_SET(1) | in sparx5_manual_injection_mode()
269 spx5_wr(QS_INJ_GRP_CFG_MODE_SET(1) | in sparx5_manual_injection_mode()
[all …]
Dsparx5_mactable.c76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
99 spx5_wr(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(addr) | in sparx5_mact_learn()
104 spx5_wr(0, sparx5, LRN_MAC_ACCESS_CFG_3); in sparx5_mact_learn()
107 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LEARN) | in sparx5_mact_learn()
169 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(1) | in sparx5_mact_getnext()
172 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET in sparx5_mact_getnext()
200 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LOOKUP) | in sparx5_mact_lookup()
227 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_UNLEARN) | in sparx5_mact_forget()
440 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(1), in sparx5_mact_pull_work()
[all …]
Dsparx5_main.c378 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); in sparx5_init_switchcore()
379 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); in sparx5_init_switchcore()
382 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
522 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
526 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
531 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); in sparx5_qlim_set()
532 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); in sparx5_qlim_set()
533 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); in sparx5_qlim_set()
534 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); in sparx5_qlim_set()
559 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, in sparx5_board_init()
[all …]
Dsparx5_port.c89 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
570 spx5_wr(DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(etype) | in sparx5_port_max_tags_set()
755 spx5_wr(DEV2G5_PCS1G_CFG_PCS_ENA_SET(1), in sparx5_port_pcs_low_set()
763 spx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(abil) | in sparx5_port_pcs_low_set()
770 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
889 spx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(tx_gap) | in sparx5_port_config_low_set()
902 spx5_wr(DEV2G5_MAC_ENA_CFG_RX_ENA | in sparx5_port_config_low_set()
1049 spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | in sparx5_port_init()
1066 spx5_wr(QSYS_ATOP_ATOP_SET(atop), in sparx5_port_init()
1071 spx5_wr(PAUSE_DISCARD, sparx5, ANA_CL_CAPTURE_BPDU_CFG(port->portno)); in sparx5_port_init()
[all …]
Dsparx5_calendar.c217 spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); in sparx5_config_auto_calendar()
229 spx5_wr(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(12), in sparx5_config_auto_calendar()
539 spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), in sparx5_dsm_calendar_update()
552 spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), in sparx5_dsm_calendar_update()
Dsparx5_main.h381 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, in spx5_wr() function
Dsparx5_ethtool.c210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); in sparx5_get_queue_sys_stats()
1172 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno) | in sparx5_config_port_stats()