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Searched refs:shared_dpll (Results 1 – 7 of 7) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c68 struct intel_shared_dpll_state *shared_dpll) in intel_atomic_duplicate_dpll_state() argument
76 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
91 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
94 return state->shared_dpll; in intel_atomic_get_shared_dpll_state()
198 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_prepare_shared_dpll()
225 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll()
271 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll()
315 struct intel_shared_dpll_state *shared_dpll; in intel_find_shared_dpll() local
318 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_find_shared_dpll()
326 if (shared_dpll[i].pipe_mask == 0) { in intel_find_shared_dpll()
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Dintel_ddi.c215 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
1495 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in adls_ddi_enable_clock()
1539 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in rkl_ddi_enable_clock()
1583 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in dg1_ddi_enable_clock()
1649 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_combo_enable_clock()
1693 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in jsl_ddi_tc_enable_clock()
1736 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_enable_clock()
1844 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in skl_ddi_enable_clock()
1912 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in hsw_ddi_enable_clock()
3706 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
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Dintel_display.c796 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); in ilk_enable_pch_transcoder()
2569 if (crtc_state->shared_dpll == in ilk_pch_enable()
3529 if (master_crtc_state->shared_dpll) in icl_ddi_bigjoiner_pre_enable()
3557 if (new_crtc_state->shared_dpll) in hsw_crtc_enable()
3950 if (crtc_state->shared_dpll) in get_crtc_power_domains()
5140 pipe_config->shared_dpll = NULL; in i9xx_get_pipe_config()
6110 pipe_config->shared_dpll = NULL; in ilk_get_pipe_config()
6183 pipe_config->shared_dpll = in ilk_get_pipe_config()
6185 pll = pipe_config->shared_dpll; in ilk_get_pipe_config()
6399 pipe_config->shared_dpll = NULL; in hsw_get_pipe_config()
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Dintel_display_types.h590 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; member
1034 struct intel_shared_dpll *shared_dpll; member
Dintel_lvds.c239 pipe_config->shared_dpll); in intel_pre_enable_lvds()
Dintel_fdi.c598 drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); in hsw_fdi_link_train()
Dicl_dsi.c700 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()