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Searched refs:set_wptr (Results 1 – 25 of 32) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/radeon/
Dradeon_asic.c195 .set_wptr = &r100_gfx_set_wptr,
345 .set_wptr = &r100_gfx_set_wptr,
359 .set_wptr = &r100_gfx_set_wptr,
916 .set_wptr = &r600_gfx_set_wptr,
929 .set_wptr = &r600_dma_set_wptr,
1014 .set_wptr = &uvd_v1_0_set_wptr,
1213 .set_wptr = &uvd_v1_0_set_wptr,
1320 .set_wptr = &r600_gfx_set_wptr,
1333 .set_wptr = &r600_dma_set_wptr,
1630 .set_wptr = &cayman_gfx_set_wptr,
[all …]
Dradeon.h1844 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); member
2757 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ring.h152 void (*set_wptr)(struct amdgpu_ring *ring); member
263 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
Djpeg_v2_5.c592 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
622 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
Dvce_v3_0.c924 .set_wptr = vce_v3_0_ring_set_wptr,
948 .set_wptr = vce_v3_0_ring_set_wptr,
Duvd_v6_0.c1558 .set_wptr = uvd_v6_0_ring_set_wptr,
1584 .set_wptr = uvd_v6_0_ring_set_wptr,
1613 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
Djpeg_v3_0.c560 .set_wptr = jpeg_v3_0_dec_ring_set_wptr,
Dvcn_v2_5.c1526 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1556 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1656 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1686 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
Dvce_v2_0.c636 .set_wptr = vce_v2_0_ring_set_wptr,
Dsdma_v4_0.c2425 .set_wptr = sdma_v4_0_ring_set_wptr,
2461 .set_wptr = sdma_v4_0_ring_set_wptr,
2493 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2525 .set_wptr = sdma_v4_0_page_ring_set_wptr,
Djpeg_v1_0.c555 .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
Duvd_v3_1.c186 .set_wptr = uvd_v3_1_ring_set_wptr,
Duvd_v4_2.c773 .set_wptr = uvd_v4_2_ring_set_wptr,
Djpeg_v2_0.c784 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
Duvd_v5_0.c881 .set_wptr = uvd_v5_0_ring_set_wptr,
Dvcn_v3_0.c1820 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1975 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
2076 .set_wptr = vcn_v3_0_enc_ring_set_wptr,
Dsi_dma.c731 .set_wptr = si_dma_ring_set_wptr,
Dvcn_v1_0.c1909 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1943 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
Duvd_v7_0.c1813 .set_wptr = uvd_v7_0_ring_set_wptr,
1846 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
Dvcn_v2_0.c2013 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2044 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
Dmes_v10_1.c81 .set_wptr = mes_v10_1_ring_set_wptr,
Dsdma_v2_4.c1147 .set_wptr = sdma_v2_4_ring_set_wptr,
Dcik_sdma.c1258 .set_wptr = cik_sdma_ring_set_wptr,
Dvce_v4_0.c1105 .set_wptr = vce_v4_0_ring_set_wptr,
Dsdma_v3_0.c1585 .set_wptr = sdma_v3_0_ring_set_wptr,

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