Home
last modified time | relevance | path

Searched refs:rvu_write64 (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_devlink.c83 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT, intr); in rvu_nix_af_rvu_intr_handler()
84 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_intr_handler()
118 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT, intr); in rvu_nix_af_rvu_gen_handler()
119 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_gen_handler()
153 rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT, intr); in rvu_nix_af_rvu_err_handler()
154 rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_err_handler()
188 rvu_write64(rvu, blkaddr, NIX_AF_RAS, intr); in rvu_nix_af_rvu_ras_handler()
189 rvu_write64(rvu, blkaddr, NIX_AF_RAS_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_ras_handler()
208 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
209 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
[all …]
Drvu_nix.c238 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); in nix_rx_sync()
249 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); in nix_rx_sync()
494 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), in rvu_mbox_handler_nix_bp_disable()
610 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), in rvu_mbox_handler_nix_bp_enable()
639 rvu_write64(rvu, blkaddr, in nix_setup_lso_tso_l3()
652 rvu_write64(rvu, blkaddr, in nix_setup_lso_tso_l3()
667 rvu_write64(rvu, blkaddr, in nix_setup_lso_tso_l4()
676 rvu_write64(rvu, blkaddr, in nix_setup_lso_tso_l4()
696 rvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63)); in nix_setup_lso()
708 rvu_write64(rvu, blkaddr, in nix_setup_lso()
[all …]
Drvu_cpt.c148 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); in rvu_mbox_handler_cpt_lf_alloc()
153 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val); in rvu_mbox_handler_cpt_lf_alloc()
177 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), 0x0); in cpt_lf_free()
179 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), 0x0); in cpt_lf_free()
282 rvu_write64(rvu, blkaddr, req->reg_offset, req->val); in rvu_mbox_handler_cpt_rd_wr_register()
400 rvu_write64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG, req->step); in cpt_rxc_time_cfg()
401 rvu_write64(rvu, blkaddr, CPT_AF_RXC_DFRG, dfrg_reg); in cpt_rxc_time_cfg()
436 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0); in cpt_lf_disable_iqueue()
442 rvu_write64(rvu, blkaddr, in cpt_lf_disable_iqueue()
499 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg); in rvu_cpt_lf_teardown()
[all …]
Drvu_npc.c96 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); in rvu_npc_set_pkind()
138 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); in npc_config_ts_kpuaction()
223 rvu_write64(rvu, blkaddr, in npc_enable_mcam_entry()
237 rvu_write64(rvu, blkaddr, in npc_clear_mcam_entry()
239 rvu_write64(rvu, blkaddr, in npc_clear_mcam_entry()
242 rvu_write64(rvu, blkaddr, in npc_clear_mcam_entry()
244 rvu_write64(rvu, blkaddr, in npc_clear_mcam_entry()
247 rvu_write64(rvu, blkaddr, in npc_clear_mcam_entry()
249 rvu_write64(rvu, blkaddr, in npc_clear_mcam_entry()
470 rvu_write64(rvu, blkaddr, in npc_config_mcam_entry()
[all …]
Drvu_npa.c36 rvu_write64(rvu, block->addr, NPA_AF_AQ_DOOR, 1); in npa_aq_enqueue_wait()
395 rvu_write64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf), cfg); in rvu_mbox_handler_npa_lf_alloc()
398 rvu_write64(rvu, blkaddr, NPA_AF_LFX_LOC_AURAS_BASE(npalf), in rvu_mbox_handler_npa_lf_alloc()
402 rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_CFG(npalf), in rvu_mbox_handler_npa_lf_alloc()
404 rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_BASE(npalf), in rvu_mbox_handler_npa_lf_alloc()
467 rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); in npa_aq_init()
470 rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); in npa_aq_init()
480 rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg); in npa_aq_init()
487 rvu_write64(rvu, block->addr, NPA_AF_BATCH_CTL, cfg); in npa_aq_init()
499 rvu_write64(rvu, block->addr, NPA_AF_AQ_CFG, AQ_SIZE); in npa_aq_init()
[all …]
Drvu_cn10k.c43 rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, BIT_ULL(0)); in lmtst_map_table_ops()
45 rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, 0x00); in lmtst_map_table_ops()
70 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova); in rvu_get_lmtaddr()
74 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val); in rvu_get_lmtaddr()
455 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg); in __rvu_nix_set_channels()
465 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg); in __rvu_nix_set_channels()
475 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg); in __rvu_nix_set_channels()
485 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg); in __rvu_nix_set_channels()
Drvu.c395 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); in rvu_update_rsrc_map()
489 rvu_write64(rvu, BLKADDR_RVUM, in rvu_setup_rvum_blk_revid()
496 rvu_write64(rvu, BLKADDR_RVUM, in rvu_clear_rvum_blk_revid()
507 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); in rvu_lf_reset()
521 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); in rvu_block_reset()
645 rvu_write64(rvu, BLKADDR_RVUM, in rvu_setup_msix_resources()
677 rvu_write64(rvu, BLKADDR_RVUM, in rvu_setup_msix_resources()
701 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); in rvu_setup_msix_resources()
711 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, in rvu_reset_msix()
1275 rvu_write64(rvu, block->addr, block->lookup_reg, val); in rvu_lookup_rsrc()
[all …]
Drvu_npc_fs.c1096 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(rule->cntr), 0x00); in npc_install_flow()
1382 rvu_write64(rvu, blkaddr, in npc_mcam_enable_flows()
Drvu.h500 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) in rvu_write64() function