Home
last modified time | relevance | path

Searched refs:rvu_read64 (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.15/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_cpt.c29 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e)); \
284 rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset); in rvu_mbox_handler_cpt_rd_wr_register()
294 rsp->ctx_mis_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_MIS_PC); in get_ctx_pc()
295 rsp->ctx_hit_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_HIT_PC); in get_ctx_pc()
296 rsp->ctx_aop_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_AOP_PC); in get_ctx_pc()
297 rsp->ctx_aop_lat_pc = rvu_read64(rvu, blkaddr, in get_ctx_pc()
299 rsp->ctx_ifetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_IFETCH_PC); in get_ctx_pc()
300 rsp->ctx_ifetch_lat_pc = rvu_read64(rvu, blkaddr, in get_ctx_pc()
302 rsp->ctx_ffetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC); in get_ctx_pc()
303 rsp->ctx_ffetch_lat_pc = rvu_read64(rvu, blkaddr, in get_ctx_pc()
[all …]
Drvu_cn10k.c26 tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); in lmtst_map_table_ops()
44 rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CTL); in lmtst_map_table_ops()
81 val = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS); in rvu_get_lmtaddr()
89 pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT0) >> 18; in rvu_get_lmtaddr()
291 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST); in rvu_set_channels_base()
292 nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); in rvu_set_channels_base()
436 u64 nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); in __rvu_nix_set_channels()
437 u64 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST); in __rvu_nix_set_channels()
451 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link)); in __rvu_nix_set_channels()
461 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link)); in __rvu_nix_set_channels()
[all …]
Drvu_npa.c26 reg = rvu_read64(rvu, block->addr, NPA_AF_AQ_STATUS); in npa_aq_enqueue_wait()
354 ctx_cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST1); in rvu_mbox_handler_npa_lf_alloc()
380 cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST); in rvu_mbox_handler_npa_lf_alloc()
389 cfg = rvu_read64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf)); in rvu_mbox_handler_npa_lf_alloc()
415 cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST); in rvu_mbox_handler_npa_lf_alloc()
420 cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL); in rvu_mbox_handler_npa_lf_alloc()
464 cfg = rvu_read64(rvu, block->addr, NPA_AF_GEN_CFG); in npa_aq_init()
474 cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); in npa_aq_init()
484 cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL); in npa_aq_init()
Drvu_debugfs.c199 #define NDC_MAX_BANK(rvu, blk_addr) (rvu_read64(rvu, \
966 req = rvu_read64(rvu, blk_addr, NDC_AF_PORTX_RTX_RWX_REQ_PC in ndc_cache_stats()
968 lat = rvu_read64(rvu, blk_addr, NDC_AF_PORTX_RTX_RWX_LAT_PC in ndc_cache_stats()
970 out_req = rvu_read64(rvu, blk_addr, in ndc_cache_stats()
973 cant_alloc = rvu_read64(rvu, blk_addr, in ndc_cache_stats()
1022 (u64)rvu_read64(rvu, blk_addr, in ndc_blk_hits_miss_stats()
1025 (u64)rvu_read64(rvu, blk_addr, in ndc_blk_hits_miss_stats()
2237 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX)); in rvu_dbg_npc_mcam_info_display()
2242 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX)); in rvu_dbg_npc_mcam_info_display()
2273 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in rvu_dbg_npc_mcam_info_display()
[all …]
Drvu.c301 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); in rvu_get_blkaddr()
309 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); in rvu_get_blkaddr()
317 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); in rvu_get_blkaddr()
325 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); in rvu_get_blkaddr()
408 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in rvu_get_pf_numvfs()
424 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in rvu_get_hwvf()
452 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in is_pf_func_valid()
552 cfg = rvu_read64(rvu, block->addr, in rvu_scan_block()
607 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); in rvu_setup_msix_resources()
616 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); in rvu_setup_msix_resources()
[all …]
Drvu_nix.c493 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); in rvu_mbox_handler_nix_bp_disable()
511 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); in rvu_nix_get_bpid()
514 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); in rvu_nix_get_bpid()
608 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); in rvu_mbox_handler_nix_bp_enable()
686 cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF; in nix_setup_lso()
690 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG); in nix_setup_lso()
803 reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS); in nix_aq_enqueue_wait()
880 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf)); in rvu_nix_blk_aq_enq_inst()
886 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG); in rvu_nix_blk_aq_enq_inst()
1279 ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3); in rvu_mbox_handler_nix_lf_alloc()
[all …]
Drvu_npc.c132 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); in npc_config_ts_kpuaction()
211 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); in is_mcam_entry_enabled()
397 return rvu_read64(rvu, blkaddr, in npc_get_default_entry_action()
520 cam1 = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
522 cam0 = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
526 cam1 = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
528 cam0 = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
533 entry->action = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
536 rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
538 *intf = rvu_read64(rvu, blkaddr, in npc_read_mcam_entry()
[all …]
Drvu_devlink.c79 intr = rvu_read64(rvu, blkaddr, NIX_AF_RVU_INT); in rvu_nix_af_rvu_intr_handler()
114 intr = rvu_read64(rvu, blkaddr, NIX_AF_GEN_INT); in rvu_nix_af_rvu_gen_handler()
149 intr = rvu_read64(rvu, blkaddr, NIX_AF_ERR_INT); in rvu_nix_af_rvu_err_handler()
184 intr = rvu_read64(rvu, blkaddr, NIX_AF_ERR_INT); in rvu_nix_af_rvu_ras_handler()
204 offs = rvu_read64(rvu, blkaddr, NIX_PRIV_AF_INT_CFG) & 0x3ff; in rvu_nix_unregister_interrupts()
236 base = rvu_read64(rvu, blkaddr, NIX_PRIV_AF_INT_CFG) & 0x3ff; in rvu_nix_register_interrupts()
723 intr = rvu_read64(rvu, blkaddr, NPA_AF_RVU_INT); in rvu_npa_af_rvu_intr_handler()
758 intr = rvu_read64(rvu, blkaddr, NPA_AF_GEN_INT); in rvu_npa_af_gen_intr_handler()
792 intr = rvu_read64(rvu, blkaddr, NPA_AF_ERR_INT); in rvu_npa_af_err_intr_handler()
827 intr = rvu_read64(rvu, blkaddr, NPA_AF_RAS); in rvu_npa_af_ras_intr_handler()
[all …]
Drvu_sdp.c104 rsp->num_chan = rvu_read64(rvu, blkaddr, NIX_AF_CONST1) & 0xFFFUL; in rvu_mbox_handler_get_sdp_chan_info()
Drvu.h505 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) in rvu_read64() function
576 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); in rvu_nix_chan_cgx()
590 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); in rvu_nix_chan_lbk()
Drvu_cgx.c929 *stat += rvu_read64(rvu, blkaddr, in rvu_cgx_nix_cuml_stats()
932 *stat += rvu_read64(rvu, blkaddr, in rvu_cgx_nix_cuml_stats()
Drvu_npc_fs.c192 cfg = rvu_read64(rvu, blkaddr, in npc_check_overlap()
520 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf)); in npc_scan_kex()
531 cfg = rvu_read64(rvu, blkaddr, in npc_scan_kex()