Searched refs:reg_ch_base (Results 1 – 4 of 4) sorted by relevance
| /Linux-v5.15/drivers/dma/ |
| D | milbeaut-xdmac.c | 71 void __iomem *reg_ch_base; member
119 writel_relaxed(val, mc->reg_ch_base + M10V_XDTBC); in milbeaut_chan_start()
122 writel_relaxed(val, mc->reg_ch_base + M10V_XDSSA); in milbeaut_chan_start()
125 writel_relaxed(val, mc->reg_ch_base + M10V_XDDSA); in milbeaut_chan_start()
127 val = readl_relaxed(mc->reg_ch_base + M10V_XDSAC); in milbeaut_chan_start()
131 writel_relaxed(val, mc->reg_ch_base + M10V_XDSAC); in milbeaut_chan_start()
133 val = readl_relaxed(mc->reg_ch_base + M10V_XDDAC); in milbeaut_chan_start()
137 writel_relaxed(val, mc->reg_ch_base + M10V_XDDAC); in milbeaut_chan_start()
140 val = readl_relaxed(mc->reg_ch_base + M10V_XDDES); in milbeaut_chan_start()
146 writel_relaxed(val, mc->reg_ch_base + M10V_XDDES); in milbeaut_chan_start()
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| D | uniphier-xdmac.c | 90 void __iomem *reg_ch_base; member
169 writel(val, xc->reg_ch_base + XDMAC_TFA); in uniphier_xdmac_chan_start()
172 writel(lower_32_bits(src_addr), xc->reg_ch_base + XDMAC_SAD); in uniphier_xdmac_chan_start()
173 writel(upper_32_bits(src_addr), xc->reg_ch_base + XDMAC_EXSAD); in uniphier_xdmac_chan_start()
175 writel(lower_32_bits(dst_addr), xc->reg_ch_base + XDMAC_DAD); in uniphier_xdmac_chan_start()
176 writel(upper_32_bits(dst_addr), xc->reg_ch_base + XDMAC_EXDAD); in uniphier_xdmac_chan_start()
180 writel(src_mode, xc->reg_ch_base + XDMAC_SADM); in uniphier_xdmac_chan_start()
181 writel(dst_mode, xc->reg_ch_base + XDMAC_DADM); in uniphier_xdmac_chan_start()
183 writel(its, xc->reg_ch_base + XDMAC_ITS); in uniphier_xdmac_chan_start()
184 writel(tnum, xc->reg_ch_base + XDMAC_TNUM); in uniphier_xdmac_chan_start()
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| D | milbeaut-hdmac.c | 71 void __iomem *reg_ch_base; member
143 writel_relaxed(src_addr, mc->reg_ch_base + MLB_HDMAC_DMACSA); in milbeaut_chan_start()
144 writel_relaxed(dest_addr, mc->reg_ch_base + MLB_HDMAC_DMACDA); in milbeaut_chan_start()
145 writel_relaxed(cb, mc->reg_ch_base + MLB_HDMAC_DMACB); in milbeaut_chan_start()
156 writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA); in milbeaut_chan_start()
158 writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA); in milbeaut_chan_start()
180 val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACB); in milbeaut_hdmac_interrupt()
182 writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB); in milbeaut_hdmac_interrupt()
185 writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB); in milbeaut_hdmac_interrupt()
232 val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA); in milbeaut_hdmac_chan_pause()
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| D | uniphier-mdmac.c | 63 void __iomem *reg_ch_base; member
130 writel(src_mode, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SRC_MODE); in uniphier_mdmac_handle()
131 writel(dest_mode, mc->reg_ch_base + UNIPHIER_MDMAC_CH_DEST_MODE); in uniphier_mdmac_handle()
132 writel(src_addr, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SRC_ADDR); in uniphier_mdmac_handle()
133 writel(dest_addr, mc->reg_ch_base + UNIPHIER_MDMAC_CH_DEST_ADDR); in uniphier_mdmac_handle()
134 writel(chunk_size, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SIZE); in uniphier_mdmac_handle()
137 writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ); in uniphier_mdmac_handle()
139 writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_EN); in uniphier_mdmac_handle()
162 writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ); in uniphier_mdmac_abort()
171 return readl_poll_timeout(mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ, in uniphier_mdmac_abort()
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