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Searched refs:regPWRSEQ1_BL_PWM_CNTL_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_4_2_0_offset.h121 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_1_2_offset.h12454 #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX … macro