| /Linux-v5.15/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v2_4.c | 282 u32 ref_and_mask = 0; in sdma_v2_4_ring_emit_hdp_flush() local
285 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
287 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
294 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v2_4_ring_emit_hdp_flush()
295 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v2_4_ring_emit_hdp_flush()
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| D | sdma_v3_0.c | 456 u32 ref_and_mask = 0; in sdma_v3_0_ring_emit_hdp_flush() local
459 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
461 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
468 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v3_0_ring_emit_hdp_flush()
469 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v3_0_ring_emit_hdp_flush()
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| D | cik_sdma.c | 253 u32 ref_and_mask; in cik_sdma_ring_emit_hdp_flush() local
256 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; in cik_sdma_ring_emit_hdp_flush()
258 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; in cik_sdma_ring_emit_hdp_flush()
263 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
264 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_ring_emit_hdp_flush()
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| D | sdma_v5_0.c | 516 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush() local
520 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; in sdma_v5_0_ring_emit_hdp_flush()
522 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; in sdma_v5_0_ring_emit_hdp_flush()
529 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_0_ring_emit_hdp_flush()
530 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_0_ring_emit_hdp_flush()
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| D | sdma_v5_2.c | 404 u32 ref_and_mask = 0; in sdma_v5_2_ring_emit_hdp_flush() local
407 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v5_2_ring_emit_hdp_flush()
414 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_2_ring_emit_hdp_flush()
415 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_2_ring_emit_hdp_flush()
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| D | sdma_v4_0.c | 928 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush() local
931 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v4_0_ring_emit_hdp_flush()
936 ref_and_mask, ref_and_mask, 10); in sdma_v4_0_ring_emit_hdp_flush()
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| D | gfx_v7_0.c | 2127 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local
2133 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2136 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2142 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush()
2151 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2152 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
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| D | gfx_v8_0.c | 6080 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local
6086 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6089 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6096 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_ring_emit_hdp_flush()
6106 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
6107 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
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| D | gfx_v9_0.c | 5309 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local
5315 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5318 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5325 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_0_ring_emit_hdp_flush()
5332 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()
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| D | gfx_v10_0.c | 8562 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local
8568 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8571 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8578 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v10_0_ring_emit_hdp_flush()
8585 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()
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| /Linux-v5.15/drivers/gpu/drm/radeon/ |
| D | cik_sdma.c | 174 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
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| D | cik.c | 3498 u32 ref_and_mask; in cik_hdp_flush_cp_ring_emit() local
3506 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3509 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3516 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
3526 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3527 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
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