1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef MBOX_H
9 #define MBOX_H
10
11 #include <linux/etherdevice.h>
12 #include <linux/sizes.h>
13
14 #include "rvu_struct.h"
15 #include "common.h"
16
17 #define MBOX_SIZE SZ_64K
18
19 /* AF/PF: PF initiated, PF/VF VF initiated */
20 #define MBOX_DOWN_RX_START 0
21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
24 /* AF/PF: AF initiated, PF/VF PF initiated */
25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
26 #define MBOX_UP_RX_SIZE SZ_1K
27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
28 #define MBOX_UP_TX_SIZE SZ_1K
29
30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
31 # error "incorrect mailbox area sizes"
32 #endif
33
34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
35
36 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */
37
38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
39
40 /* Mailbox directions */
41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
49
50 struct otx2_mbox_dev {
51 void *mbase; /* This dev's mbox region */
52 void *hwbase;
53 spinlock_t mbox_lock;
54 u16 msg_size; /* Total msg size to be sent */
55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
56 u16 num_msgs; /* No of msgs sent or waiting for response */
57 u16 msgs_acked; /* No of msgs for which response is received */
58 };
59
60 struct otx2_mbox {
61 struct pci_dev *pdev;
62 void *hwbase; /* Mbox region advertised by HW */
63 void *reg_base;/* CSR base for this dev */
64 u64 trigger; /* Trigger mbox notification */
65 u16 tr_shift; /* Mbox trigger shift */
66 u64 rx_start; /* Offset of Rx region in mbox memory */
67 u64 tx_start; /* Offset of Tx region in mbox memory */
68 u16 rx_size; /* Size of Rx region */
69 u16 tx_size; /* Size of Tx region */
70 u16 ndevs; /* The number of peers */
71 struct otx2_mbox_dev *dev;
72 };
73
74 /* Header which precedes all mbox messages */
75 struct mbox_hdr {
76 u64 msg_size; /* Total msgs size embedded */
77 u16 num_msgs; /* No of msgs embedded */
78 };
79
80 /* Header which precedes every msg and is also part of it */
81 struct mbox_msghdr {
82 u16 pcifunc; /* Who's sending this msg */
83 u16 id; /* Mbox message ID */
84 #define OTX2_MBOX_REQ_SIG (0xdead)
85 #define OTX2_MBOX_RSP_SIG (0xbeef)
86 u16 sig; /* Signature, for validating corrupted msgs */
87 #define OTX2_MBOX_VERSION (0x0009)
88 u16 ver; /* Version of msg's structure for this ID */
89 u16 next_msgoff; /* Offset of next msg within mailbox region */
90 int rc; /* Msg process'ed response code */
91 };
92
93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 struct pci_dev *pdev, void __force *reg_base,
98 int direction, int ndevs);
99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
100 struct pci_dev *pdev, void __force *reg_base,
101 int direction, int ndevs);
102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
106 int size, int size_rsp);
107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
108 struct mbox_msghdr *msg);
109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
111 u16 pcifunc, u16 id);
112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
113 const char *otx2_mbox_id2name(u16 id);
otx2_mbox_alloc_msg(struct otx2_mbox * mbox,int devid,int size)114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
115 int devid, int size)
116 {
117 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
118 }
119
120 /* Mailbox message types */
121 #define MBOX_MSG_MASK 0xFFFF
122 #define MBOX_MSG_INVALID 0xFFFE
123 #define MBOX_MSG_MAX 0xFFFF
124
125 #define MBOX_MESSAGES \
126 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
127 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
130 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
131 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
132 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
133 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
134 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
135 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
136 msg_rsp) \
137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
143 cgx_mac_addr_set_or_get) \
144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
145 cgx_mac_addr_set_or_get) \
146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
156 cgx_pause_frm_cfg) \
157 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
158 M(CGX_FEC_STATS, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
159 M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
160 M(CGX_FW_DATA_GET, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
161 M(CGX_SET_LINK_MODE, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\
162 cgx_set_link_mode_rsp) \
163 M(CGX_FEATURES_GET, 0x215, cgx_features_get, msg_req, \
164 cgx_features_info_msg) \
165 M(RPM_STATS, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \
166 M(CGX_MAC_ADDR_ADD, 0x217, cgx_mac_addr_add, cgx_mac_addr_add_req, \
167 cgx_mac_addr_add_rsp) \
168 M(CGX_MAC_ADDR_DEL, 0x218, cgx_mac_addr_del, cgx_mac_addr_del_req, \
169 msg_rsp) \
170 M(CGX_MAC_MAX_ENTRIES_GET, 0x219, cgx_mac_max_entries_get, msg_req, \
171 cgx_max_dmac_entries_get_rsp) \
172 M(CGX_MAC_ADDR_RESET, 0x21A, cgx_mac_addr_reset, msg_req, msg_rsp) \
173 M(CGX_MAC_ADDR_UPDATE, 0x21B, cgx_mac_addr_update, cgx_mac_addr_update_req, \
174 msg_rsp) \
175 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
176 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
177 npa_lf_alloc_req, npa_lf_alloc_rsp) \
178 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
179 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
180 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
181 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
182 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
183 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
184 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
185 msg_rsp) \
186 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
187 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
188 cpt_rd_wr_reg_msg) \
189 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
190 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
191 msg_rsp) \
192 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
193 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
194 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
195 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
196 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
197 npc_mcam_alloc_entry_rsp) \
198 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
199 npc_mcam_free_entry_req, msg_rsp) \
200 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
201 npc_mcam_write_entry_req, msg_rsp) \
202 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
203 npc_mcam_ena_dis_entry_req, msg_rsp) \
204 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
205 npc_mcam_ena_dis_entry_req, msg_rsp) \
206 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
207 npc_mcam_shift_entry_rsp) \
208 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
209 npc_mcam_alloc_counter_req, \
210 npc_mcam_alloc_counter_rsp) \
211 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
212 npc_mcam_oper_counter_req, msg_rsp) \
213 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
214 npc_mcam_unmap_counter_req, msg_rsp) \
215 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
216 npc_mcam_oper_counter_req, msg_rsp) \
217 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
218 npc_mcam_oper_counter_req, \
219 npc_mcam_oper_counter_rsp) \
220 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
221 npc_mcam_alloc_and_write_entry_req, \
222 npc_mcam_alloc_and_write_entry_rsp) \
223 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
224 msg_req, npc_get_kex_cfg_rsp) \
225 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
226 npc_install_flow_req, npc_install_flow_rsp) \
227 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
228 npc_delete_flow_req, msg_rsp) \
229 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
230 npc_mcam_read_entry_req, \
231 npc_mcam_read_entry_rsp) \
232 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
233 msg_req, npc_mcam_read_base_rule_rsp) \
234 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
235 npc_mcam_get_stats_req, \
236 npc_mcam_get_stats_rsp) \
237 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
238 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
239 nix_lf_alloc_req, nix_lf_alloc_rsp) \
240 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
241 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
242 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
243 hwctx_disable_req, msg_rsp) \
244 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
245 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
246 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
247 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
248 nix_txschq_config) \
249 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
250 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
251 nix_vtag_config_rsp) \
252 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
253 nix_rss_flowkey_cfg, \
254 nix_rss_flowkey_cfg_rsp) \
255 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
256 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
257 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
258 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
259 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
260 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
261 nix_mark_format_cfg, \
262 nix_mark_format_cfg_rsp) \
263 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
264 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
265 nix_lso_format_cfg, \
266 nix_lso_format_cfg_rsp) \
267 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
268 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
269 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
270 nix_bp_cfg_rsp) \
271 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
272 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
273 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
274 nix_cn10k_aq_enq_rsp) \
275 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
276 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
277 nix_bandprof_alloc_rsp) \
278 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
279 msg_rsp) \
280 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
281 nix_bandprof_get_hwinfo_rsp)
282
283 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
284 #define MBOX_UP_CGX_MESSAGES \
285 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
286
287 enum {
288 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
289 MBOX_MESSAGES
290 MBOX_UP_CGX_MESSAGES
291 #undef M
292 };
293
294 /* Mailbox message formats */
295
296 #define RVU_DEFAULT_PF_FUNC 0xFFFF
297
298 /* Generic request msg used for those mbox messages which
299 * don't send any data in the request.
300 */
301 struct msg_req {
302 struct mbox_msghdr hdr;
303 };
304
305 /* Generic response msg used an ack or response for those mbox
306 * messages which don't have a specific rsp msg format.
307 */
308 struct msg_rsp {
309 struct mbox_msghdr hdr;
310 };
311
312 /* RVU mailbox error codes
313 * Range 256 - 300.
314 */
315 enum rvu_af_status {
316 RVU_INVALID_VF_ID = -256,
317 };
318
319 struct ready_msg_rsp {
320 struct mbox_msghdr hdr;
321 u16 sclk_freq; /* SCLK frequency (in MHz) */
322 u16 rclk_freq; /* RCLK frequency (in MHz) */
323 };
324
325 /* Structure for requesting resource provisioning.
326 * 'modify' flag to be used when either requesting more
327 * or to detach partial of a certain resource type.
328 * Rest of the fields specify how many of what type to
329 * be attached.
330 * To request LFs from two blocks of same type this mailbox
331 * can be sent twice as below:
332 * struct rsrc_attach *attach;
333 * .. Allocate memory for message ..
334 * attach->cptlfs = 3; <3 LFs from CPT0>
335 * .. Send message ..
336 * .. Allocate memory for message ..
337 * attach->modify = 1;
338 * attach->cpt_blkaddr = BLKADDR_CPT1;
339 * attach->cptlfs = 2; <2 LFs from CPT1>
340 * .. Send message ..
341 */
342 struct rsrc_attach {
343 struct mbox_msghdr hdr;
344 u8 modify:1;
345 u8 npalf:1;
346 u8 nixlf:1;
347 u16 sso;
348 u16 ssow;
349 u16 timlfs;
350 u16 cptlfs;
351 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
352 };
353
354 /* Structure for relinquishing resources.
355 * 'partial' flag to be used when relinquishing all resources
356 * but only of a certain type. If not set, all resources of all
357 * types provisioned to the RVU function will be detached.
358 */
359 struct rsrc_detach {
360 struct mbox_msghdr hdr;
361 u8 partial:1;
362 u8 npalf:1;
363 u8 nixlf:1;
364 u8 sso:1;
365 u8 ssow:1;
366 u8 timlfs:1;
367 u8 cptlfs:1;
368 };
369
370 /* Number of resources available to the caller.
371 * In reply to MBOX_MSG_FREE_RSRC_CNT.
372 */
373 struct free_rsrcs_rsp {
374 struct mbox_msghdr hdr;
375 u16 schq[NIX_TXSCH_LVL_CNT];
376 u16 sso;
377 u16 tim;
378 u16 ssow;
379 u16 cpt;
380 u8 npa;
381 u8 nix;
382 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
383 u8 nix1;
384 u8 cpt1;
385 u8 ree0;
386 u8 ree1;
387 };
388
389 #define MSIX_VECTOR_INVALID 0xFFFF
390 #define MAX_RVU_BLKLF_CNT 256
391
392 struct msix_offset_rsp {
393 struct mbox_msghdr hdr;
394 u16 npa_msixoff;
395 u16 nix_msixoff;
396 u16 sso;
397 u16 ssow;
398 u16 timlfs;
399 u16 cptlfs;
400 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
401 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
402 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
403 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
404 u16 cpt1_lfs;
405 u16 ree0_lfs;
406 u16 ree1_lfs;
407 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
408 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
409 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
410 };
411
412 struct get_hw_cap_rsp {
413 struct mbox_msghdr hdr;
414 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
415 u8 nix_shaping; /* Is shaping and coloring supported */
416 };
417
418 /* CGX mbox message formats */
419
420 struct cgx_stats_rsp {
421 struct mbox_msghdr hdr;
422 #define CGX_RX_STATS_COUNT 9
423 #define CGX_TX_STATS_COUNT 18
424 u64 rx_stats[CGX_RX_STATS_COUNT];
425 u64 tx_stats[CGX_TX_STATS_COUNT];
426 };
427
428 struct cgx_fec_stats_rsp {
429 struct mbox_msghdr hdr;
430 u64 fec_corr_blks;
431 u64 fec_uncorr_blks;
432 };
433 /* Structure for requesting the operation for
434 * setting/getting mac address in the CGX interface
435 */
436 struct cgx_mac_addr_set_or_get {
437 struct mbox_msghdr hdr;
438 u8 mac_addr[ETH_ALEN];
439 };
440
441 /* Structure for requesting the operation to
442 * add DMAC filter entry into CGX interface
443 */
444 struct cgx_mac_addr_add_req {
445 struct mbox_msghdr hdr;
446 u8 mac_addr[ETH_ALEN];
447 };
448
449 /* Structure for response against the operation to
450 * add DMAC filter entry into CGX interface
451 */
452 struct cgx_mac_addr_add_rsp {
453 struct mbox_msghdr hdr;
454 u8 index;
455 };
456
457 /* Structure for requesting the operation to
458 * delete DMAC filter entry from CGX interface
459 */
460 struct cgx_mac_addr_del_req {
461 struct mbox_msghdr hdr;
462 u8 index;
463 };
464
465 /* Structure for response against the operation to
466 * get maximum supported DMAC filter entries
467 */
468 struct cgx_max_dmac_entries_get_rsp {
469 struct mbox_msghdr hdr;
470 u8 max_dmac_filters;
471 };
472
473 struct cgx_link_user_info {
474 uint64_t link_up:1;
475 uint64_t full_duplex:1;
476 uint64_t lmac_type_id:4;
477 uint64_t speed:20; /* speed in Mbps */
478 uint64_t an:1; /* AN supported or not */
479 uint64_t fec:2; /* FEC type if enabled else 0 */
480 #define LMACTYPE_STR_LEN 16
481 char lmac_type[LMACTYPE_STR_LEN];
482 };
483
484 struct cgx_link_info_msg {
485 struct mbox_msghdr hdr;
486 struct cgx_link_user_info link_info;
487 };
488
489 struct cgx_pause_frm_cfg {
490 struct mbox_msghdr hdr;
491 u8 set;
492 /* set = 1 if the request is to config pause frames */
493 /* set = 0 if the request is to fetch pause frames config */
494 u8 rx_pause;
495 u8 tx_pause;
496 };
497
498 enum fec_type {
499 OTX2_FEC_NONE,
500 OTX2_FEC_BASER,
501 OTX2_FEC_RS,
502 OTX2_FEC_STATS_CNT = 2,
503 OTX2_FEC_OFF,
504 };
505
506 struct fec_mode {
507 struct mbox_msghdr hdr;
508 int fec;
509 };
510
511 struct sfp_eeprom_s {
512 #define SFP_EEPROM_SIZE 256
513 u16 sff_id;
514 u8 buf[SFP_EEPROM_SIZE];
515 u64 reserved;
516 };
517
518 struct phy_s {
519 struct {
520 u64 can_change_mod_type:1;
521 u64 mod_type:1;
522 u64 has_fec_stats:1;
523 } misc;
524 struct fec_stats_s {
525 u32 rsfec_corr_cws;
526 u32 rsfec_uncorr_cws;
527 u32 brfec_corr_blks;
528 u32 brfec_uncorr_blks;
529 } fec_stats;
530 };
531
532 struct cgx_lmac_fwdata_s {
533 u16 rw_valid;
534 u64 supported_fec;
535 u64 supported_an;
536 u64 supported_link_modes;
537 /* only applicable if AN is supported */
538 u64 advertised_fec;
539 u64 advertised_link_modes;
540 /* Only applicable if SFP/QSFP slot is present */
541 struct sfp_eeprom_s sfp_eeprom;
542 struct phy_s phy;
543 #define LMAC_FWDATA_RESERVED_MEM 1021
544 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
545 };
546
547 struct cgx_fw_data {
548 struct mbox_msghdr hdr;
549 struct cgx_lmac_fwdata_s fwdata;
550 };
551
552 struct cgx_set_link_mode_args {
553 u32 speed;
554 u8 duplex;
555 u8 an;
556 u8 ports;
557 u64 mode;
558 };
559
560 struct cgx_set_link_mode_req {
561 #define AUTONEG_UNKNOWN 0xff
562 struct mbox_msghdr hdr;
563 struct cgx_set_link_mode_args args;
564 };
565
566 struct cgx_set_link_mode_rsp {
567 struct mbox_msghdr hdr;
568 int status;
569 };
570
571 struct cgx_mac_addr_update_req {
572 struct mbox_msghdr hdr;
573 u8 mac_addr[ETH_ALEN];
574 u8 index;
575 };
576
577 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
578 #define RVU_LMAC_FEAT_PTP BIT_ULL(1) /* precision time protocol */
579 #define RVU_MAC_VERSION BIT_ULL(2)
580 #define RVU_MAC_CGX BIT_ULL(3)
581 #define RVU_MAC_RPM BIT_ULL(4)
582
583 struct cgx_features_info_msg {
584 struct mbox_msghdr hdr;
585 u64 lmac_features;
586 };
587
588 struct rpm_stats_rsp {
589 struct mbox_msghdr hdr;
590 #define RPM_RX_STATS_COUNT 43
591 #define RPM_TX_STATS_COUNT 34
592 u64 rx_stats[RPM_RX_STATS_COUNT];
593 u64 tx_stats[RPM_TX_STATS_COUNT];
594 };
595
596 /* NPA mbox message formats */
597
598 /* NPA mailbox error codes
599 * Range 301 - 400.
600 */
601 enum npa_af_status {
602 NPA_AF_ERR_PARAM = -301,
603 NPA_AF_ERR_AQ_FULL = -302,
604 NPA_AF_ERR_AQ_ENQUEUE = -303,
605 NPA_AF_ERR_AF_LF_INVALID = -304,
606 NPA_AF_ERR_AF_LF_ALLOC = -305,
607 NPA_AF_ERR_LF_RESET = -306,
608 };
609
610 /* For NPA LF context alloc and init */
611 struct npa_lf_alloc_req {
612 struct mbox_msghdr hdr;
613 int node;
614 int aura_sz; /* No of auras */
615 u32 nr_pools; /* No of pools */
616 u64 way_mask;
617 };
618
619 struct npa_lf_alloc_rsp {
620 struct mbox_msghdr hdr;
621 u32 stack_pg_ptrs; /* No of ptrs per stack page */
622 u32 stack_pg_bytes; /* Size of stack page */
623 u16 qints; /* NPA_AF_CONST::QINTS */
624 u8 cache_lines; /*BATCH ALLOC DMA */
625 };
626
627 /* NPA AQ enqueue msg */
628 struct npa_aq_enq_req {
629 struct mbox_msghdr hdr;
630 u32 aura_id;
631 u8 ctype;
632 u8 op;
633 union {
634 /* Valid when op == WRITE/INIT and ctype == AURA.
635 * LF fills the pool_id in aura.pool_addr. AF will translate
636 * the pool_id to pool context pointer.
637 */
638 struct npa_aura_s aura;
639 /* Valid when op == WRITE/INIT and ctype == POOL */
640 struct npa_pool_s pool;
641 };
642 /* Mask data when op == WRITE (1=write, 0=don't write) */
643 union {
644 /* Valid when op == WRITE and ctype == AURA */
645 struct npa_aura_s aura_mask;
646 /* Valid when op == WRITE and ctype == POOL */
647 struct npa_pool_s pool_mask;
648 };
649 };
650
651 struct npa_aq_enq_rsp {
652 struct mbox_msghdr hdr;
653 union {
654 /* Valid when op == READ and ctype == AURA */
655 struct npa_aura_s aura;
656 /* Valid when op == READ and ctype == POOL */
657 struct npa_pool_s pool;
658 };
659 };
660
661 /* Disable all contexts of type 'ctype' */
662 struct hwctx_disable_req {
663 struct mbox_msghdr hdr;
664 u8 ctype;
665 };
666
667 /* NIX mbox message formats */
668
669 /* NIX mailbox error codes
670 * Range 401 - 500.
671 */
672 enum nix_af_status {
673 NIX_AF_ERR_PARAM = -401,
674 NIX_AF_ERR_AQ_FULL = -402,
675 NIX_AF_ERR_AQ_ENQUEUE = -403,
676 NIX_AF_ERR_AF_LF_INVALID = -404,
677 NIX_AF_ERR_AF_LF_ALLOC = -405,
678 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
679 NIX_AF_ERR_TLX_INVALID = -407,
680 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
681 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
682 NIX_AF_ERR_FRS_INVALID = -410,
683 NIX_AF_ERR_RX_LINK_INVALID = -411,
684 NIX_AF_INVAL_TXSCHQ_CFG = -412,
685 NIX_AF_SMQ_FLUSH_FAILED = -413,
686 NIX_AF_ERR_LF_RESET = -414,
687 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
688 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
689 NIX_AF_ERR_MARK_CFG_FAIL = -417,
690 NIX_AF_ERR_LSO_CFG_FAIL = -418,
691 NIX_AF_INVAL_NPA_PF_FUNC = -419,
692 NIX_AF_INVAL_SSO_PF_FUNC = -420,
693 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
694 NIX_AF_ERR_RX_VTAG_INUSE = -422,
695 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
696 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
697 NIX_AF_ERR_INVALID_NIXBLK = -425,
698 NIX_AF_ERR_INVALID_BANDPROF = -426,
699 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
700 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
701 };
702
703 /* For NIX RX vtag action */
704 enum nix_rx_vtag0_type {
705 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
706 NIX_AF_LFX_RX_VTAG_TYPE1,
707 NIX_AF_LFX_RX_VTAG_TYPE2,
708 NIX_AF_LFX_RX_VTAG_TYPE3,
709 NIX_AF_LFX_RX_VTAG_TYPE4,
710 NIX_AF_LFX_RX_VTAG_TYPE5,
711 NIX_AF_LFX_RX_VTAG_TYPE6,
712 NIX_AF_LFX_RX_VTAG_TYPE7,
713 };
714
715 /* For NIX LF context alloc and init */
716 struct nix_lf_alloc_req {
717 struct mbox_msghdr hdr;
718 int node;
719 u32 rq_cnt; /* No of receive queues */
720 u32 sq_cnt; /* No of send queues */
721 u32 cq_cnt; /* No of completion queues */
722 u8 xqe_sz;
723 u16 rss_sz;
724 u8 rss_grps;
725 u16 npa_func;
726 u16 sso_func;
727 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
728 u64 way_mask;
729 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
730 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
731 u64 flags;
732 };
733
734 struct nix_lf_alloc_rsp {
735 struct mbox_msghdr hdr;
736 u16 sqb_size;
737 u16 rx_chan_base;
738 u16 tx_chan_base;
739 u8 rx_chan_cnt; /* total number of RX channels */
740 u8 tx_chan_cnt; /* total number of TX channels */
741 u8 lso_tsov4_idx;
742 u8 lso_tsov6_idx;
743 u8 mac_addr[ETH_ALEN];
744 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
745 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
746 u16 cints; /* NIX_AF_CONST2::CINTS */
747 u16 qints; /* NIX_AF_CONST2::QINTS */
748 u8 cgx_links; /* No. of CGX links present in HW */
749 u8 lbk_links; /* No. of LBK links present in HW */
750 u8 sdp_links; /* No. of SDP links present in HW */
751 u8 tx_link; /* Transmit channel link number */
752 };
753
754 struct nix_lf_free_req {
755 struct mbox_msghdr hdr;
756 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
757 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
758 u64 flags;
759 };
760
761 /* CN10K NIX AQ enqueue msg */
762 struct nix_cn10k_aq_enq_req {
763 struct mbox_msghdr hdr;
764 u32 qidx;
765 u8 ctype;
766 u8 op;
767 union {
768 struct nix_cn10k_rq_ctx_s rq;
769 struct nix_cn10k_sq_ctx_s sq;
770 struct nix_cq_ctx_s cq;
771 struct nix_rsse_s rss;
772 struct nix_rx_mce_s mce;
773 struct nix_bandprof_s prof;
774 };
775 union {
776 struct nix_cn10k_rq_ctx_s rq_mask;
777 struct nix_cn10k_sq_ctx_s sq_mask;
778 struct nix_cq_ctx_s cq_mask;
779 struct nix_rsse_s rss_mask;
780 struct nix_rx_mce_s mce_mask;
781 struct nix_bandprof_s prof_mask;
782 };
783 };
784
785 struct nix_cn10k_aq_enq_rsp {
786 struct mbox_msghdr hdr;
787 union {
788 struct nix_cn10k_rq_ctx_s rq;
789 struct nix_cn10k_sq_ctx_s sq;
790 struct nix_cq_ctx_s cq;
791 struct nix_rsse_s rss;
792 struct nix_rx_mce_s mce;
793 struct nix_bandprof_s prof;
794 };
795 };
796
797 /* NIX AQ enqueue msg */
798 struct nix_aq_enq_req {
799 struct mbox_msghdr hdr;
800 u32 qidx;
801 u8 ctype;
802 u8 op;
803 union {
804 struct nix_rq_ctx_s rq;
805 struct nix_sq_ctx_s sq;
806 struct nix_cq_ctx_s cq;
807 struct nix_rsse_s rss;
808 struct nix_rx_mce_s mce;
809 u64 prof;
810 };
811 union {
812 struct nix_rq_ctx_s rq_mask;
813 struct nix_sq_ctx_s sq_mask;
814 struct nix_cq_ctx_s cq_mask;
815 struct nix_rsse_s rss_mask;
816 struct nix_rx_mce_s mce_mask;
817 u64 prof_mask;
818 };
819 };
820
821 struct nix_aq_enq_rsp {
822 struct mbox_msghdr hdr;
823 union {
824 struct nix_rq_ctx_s rq;
825 struct nix_sq_ctx_s sq;
826 struct nix_cq_ctx_s cq;
827 struct nix_rsse_s rss;
828 struct nix_rx_mce_s mce;
829 struct nix_bandprof_s prof;
830 };
831 };
832
833 /* Tx scheduler/shaper mailbox messages */
834
835 #define MAX_TXSCHQ_PER_FUNC 128
836
837 struct nix_txsch_alloc_req {
838 struct mbox_msghdr hdr;
839 /* Scheduler queue count request at each level */
840 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
841 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
842 };
843
844 struct nix_txsch_alloc_rsp {
845 struct mbox_msghdr hdr;
846 /* Scheduler queue count allocated at each level */
847 u16 schq_contig[NIX_TXSCH_LVL_CNT];
848 u16 schq[NIX_TXSCH_LVL_CNT];
849 /* Scheduler queue list allocated at each level */
850 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
851 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
852 u8 aggr_level; /* Traffic aggregation scheduler level */
853 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
854 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
855 };
856
857 struct nix_txsch_free_req {
858 struct mbox_msghdr hdr;
859 #define TXSCHQ_FREE_ALL BIT_ULL(0)
860 u16 flags;
861 /* Scheduler queue level to be freed */
862 u16 schq_lvl;
863 /* List of scheduler queues to be freed */
864 u16 schq;
865 };
866
867 struct nix_txschq_config {
868 struct mbox_msghdr hdr;
869 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
870 u8 read;
871 #define TXSCHQ_IDX_SHIFT 16
872 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
873 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
874 u8 num_regs;
875 #define MAX_REGS_PER_MBOX_MSG 20
876 u64 reg[MAX_REGS_PER_MBOX_MSG];
877 u64 regval[MAX_REGS_PER_MBOX_MSG];
878 /* All 0's => overwrite with new value */
879 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
880 };
881
882 struct nix_vtag_config {
883 struct mbox_msghdr hdr;
884 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
885 u8 vtag_size;
886 /* cfg_type is '0' for tx vlan cfg
887 * cfg_type is '1' for rx vlan cfg
888 */
889 u8 cfg_type;
890 union {
891 /* valid when cfg_type is '0' */
892 struct {
893 u64 vtag0;
894 u64 vtag1;
895
896 /* cfg_vtag0 & cfg_vtag1 fields are valid
897 * when free_vtag0 & free_vtag1 are '0's.
898 */
899 /* cfg_vtag0 = 1 to configure vtag0 */
900 u8 cfg_vtag0 :1;
901 /* cfg_vtag1 = 1 to configure vtag1 */
902 u8 cfg_vtag1 :1;
903
904 /* vtag0_idx & vtag1_idx are only valid when
905 * both cfg_vtag0 & cfg_vtag1 are '0's,
906 * these fields are used along with free_vtag0
907 * & free_vtag1 to free the nix lf's tx_vlan
908 * configuration.
909 *
910 * Denotes the indices of tx_vtag def registers
911 * that needs to be cleared and freed.
912 */
913 int vtag0_idx;
914 int vtag1_idx;
915
916 /* free_vtag0 & free_vtag1 fields are valid
917 * when cfg_vtag0 & cfg_vtag1 are '0's.
918 */
919 /* free_vtag0 = 1 clears vtag0 configuration
920 * vtag0_idx denotes the index to be cleared.
921 */
922 u8 free_vtag0 :1;
923 /* free_vtag1 = 1 clears vtag1 configuration
924 * vtag1_idx denotes the index to be cleared.
925 */
926 u8 free_vtag1 :1;
927 } tx;
928
929 /* valid when cfg_type is '1' */
930 struct {
931 /* rx vtag type index, valid values are in 0..7 range */
932 u8 vtag_type;
933 /* rx vtag strip */
934 u8 strip_vtag :1;
935 /* rx vtag capture */
936 u8 capture_vtag :1;
937 } rx;
938 };
939 };
940
941 struct nix_vtag_config_rsp {
942 struct mbox_msghdr hdr;
943 int vtag0_idx;
944 int vtag1_idx;
945 /* Indices of tx_vtag def registers used to configure
946 * tx vtag0 & vtag1 headers, these indices are valid
947 * when nix_vtag_config mbox requested for vtag0 and/
948 * or vtag1 configuration.
949 */
950 };
951
952 struct nix_rss_flowkey_cfg {
953 struct mbox_msghdr hdr;
954 int mcam_index; /* MCAM entry index to modify */
955 #define NIX_FLOW_KEY_TYPE_PORT BIT(0)
956 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
957 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
958 #define NIX_FLOW_KEY_TYPE_TCP BIT(3)
959 #define NIX_FLOW_KEY_TYPE_UDP BIT(4)
960 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
961 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
962 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
963 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
964 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
965 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
966 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
967 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
968 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
969 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
970 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
971 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
972 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
973 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
974 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
975 #define NIX_FLOW_KEY_TYPE_AH BIT(22)
976 #define NIX_FLOW_KEY_TYPE_ESP BIT(23)
977 u32 flowkey_cfg; /* Flowkey types selected */
978 u8 group; /* RSS context or group */
979 };
980
981 struct nix_rss_flowkey_cfg_rsp {
982 struct mbox_msghdr hdr;
983 u8 alg_idx; /* Selected algo index */
984 };
985
986 struct nix_set_mac_addr {
987 struct mbox_msghdr hdr;
988 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
989 };
990
991 struct nix_get_mac_addr_rsp {
992 struct mbox_msghdr hdr;
993 u8 mac_addr[ETH_ALEN];
994 };
995
996 struct nix_mark_format_cfg {
997 struct mbox_msghdr hdr;
998 u8 offset;
999 u8 y_mask;
1000 u8 y_val;
1001 u8 r_mask;
1002 u8 r_val;
1003 };
1004
1005 struct nix_mark_format_cfg_rsp {
1006 struct mbox_msghdr hdr;
1007 u8 mark_format_idx;
1008 };
1009
1010 struct nix_rx_mode {
1011 struct mbox_msghdr hdr;
1012 #define NIX_RX_MODE_UCAST BIT(0)
1013 #define NIX_RX_MODE_PROMISC BIT(1)
1014 #define NIX_RX_MODE_ALLMULTI BIT(2)
1015 #define NIX_RX_MODE_USE_MCE BIT(3)
1016 u16 mode;
1017 };
1018
1019 struct nix_rx_cfg {
1020 struct mbox_msghdr hdr;
1021 #define NIX_RX_OL3_VERIFY BIT(0)
1022 #define NIX_RX_OL4_VERIFY BIT(1)
1023 u8 len_verify; /* Outer L3/L4 len check */
1024 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1025 u8 csum_verify; /* Outer L4 checksum verification */
1026 };
1027
1028 struct nix_frs_cfg {
1029 struct mbox_msghdr hdr;
1030 u8 update_smq; /* Update SMQ's min/max lens */
1031 u8 update_minlen; /* Set minlen also */
1032 u8 sdp_link; /* Set SDP RX link */
1033 u16 maxlen;
1034 u16 minlen;
1035 };
1036
1037 struct nix_lso_format_cfg {
1038 struct mbox_msghdr hdr;
1039 u64 field_mask;
1040 #define NIX_LSO_FIELD_MAX 8
1041 u64 fields[NIX_LSO_FIELD_MAX];
1042 };
1043
1044 struct nix_lso_format_cfg_rsp {
1045 struct mbox_msghdr hdr;
1046 u8 lso_format_idx;
1047 };
1048
1049 struct nix_bp_cfg_req {
1050 struct mbox_msghdr hdr;
1051 u16 chan_base; /* Starting channel number */
1052 u8 chan_cnt; /* Number of channels */
1053 u8 bpid_per_chan;
1054 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1055 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1056 };
1057
1058 /* PF can be mapped to either CGX or LBK interface,
1059 * so maximum 64 channels are possible.
1060 */
1061 #define NIX_MAX_BPID_CHAN 64
1062 struct nix_bp_cfg_rsp {
1063 struct mbox_msghdr hdr;
1064 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1065 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1066 };
1067
1068 struct nix_hw_info {
1069 struct mbox_msghdr hdr;
1070 u16 rsvs16;
1071 u16 max_mtu;
1072 u16 min_mtu;
1073 u32 rpm_dwrr_mtu;
1074 u32 sdp_dwrr_mtu;
1075 u64 rsvd[16]; /* Add reserved fields for future expansion */
1076 };
1077
1078 struct nix_bandprof_alloc_req {
1079 struct mbox_msghdr hdr;
1080 /* Count of profiles needed per layer */
1081 u16 prof_count[BAND_PROF_NUM_LAYERS];
1082 };
1083
1084 struct nix_bandprof_alloc_rsp {
1085 struct mbox_msghdr hdr;
1086 u16 prof_count[BAND_PROF_NUM_LAYERS];
1087
1088 /* There is no need to allocate morethan 1 bandwidth profile
1089 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1090 * profiles to 64 per PF_FUNC.
1091 */
1092 #define MAX_BANDPROF_PER_PFFUNC 64
1093 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1094 };
1095
1096 struct nix_bandprof_free_req {
1097 struct mbox_msghdr hdr;
1098 u8 free_all;
1099 u16 prof_count[BAND_PROF_NUM_LAYERS];
1100 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1101 };
1102
1103 struct nix_bandprof_get_hwinfo_rsp {
1104 struct mbox_msghdr hdr;
1105 u16 prof_count[BAND_PROF_NUM_LAYERS];
1106 u32 policer_timeunit;
1107 };
1108
1109 /* NPC mbox message structs */
1110
1111 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1112 #define NPC_MCAM_INVALID_MAP 0xFFFF
1113
1114 /* NPC mailbox error codes
1115 * Range 701 - 800.
1116 */
1117 enum npc_af_status {
1118 NPC_MCAM_INVALID_REQ = -701,
1119 NPC_MCAM_ALLOC_DENIED = -702,
1120 NPC_MCAM_ALLOC_FAILED = -703,
1121 NPC_MCAM_PERM_DENIED = -704,
1122 NPC_FLOW_INTF_INVALID = -707,
1123 NPC_FLOW_CHAN_INVALID = -708,
1124 NPC_FLOW_NO_NIXLF = -709,
1125 NPC_FLOW_NOT_SUPPORTED = -710,
1126 NPC_FLOW_VF_PERM_DENIED = -711,
1127 NPC_FLOW_VF_NOT_INIT = -712,
1128 NPC_FLOW_VF_OVERLAP = -713,
1129 };
1130
1131 struct npc_mcam_alloc_entry_req {
1132 struct mbox_msghdr hdr;
1133 #define NPC_MAX_NONCONTIG_ENTRIES 256
1134 u8 contig; /* Contiguous entries ? */
1135 #define NPC_MCAM_ANY_PRIO 0
1136 #define NPC_MCAM_LOWER_PRIO 1
1137 #define NPC_MCAM_HIGHER_PRIO 2
1138 u8 priority; /* Lower or higher w.r.t ref_entry */
1139 u16 ref_entry;
1140 u16 count; /* Number of entries requested */
1141 };
1142
1143 struct npc_mcam_alloc_entry_rsp {
1144 struct mbox_msghdr hdr;
1145 u16 entry; /* Entry allocated or start index if contiguous.
1146 * Invalid incase of non-contiguous.
1147 */
1148 u16 count; /* Number of entries allocated */
1149 u16 free_count; /* Number of entries available */
1150 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1151 };
1152
1153 struct npc_mcam_free_entry_req {
1154 struct mbox_msghdr hdr;
1155 u16 entry; /* Entry index to be freed */
1156 u8 all; /* If all entries allocated to this PFVF to be freed */
1157 };
1158
1159 struct mcam_entry {
1160 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1161 u64 kw[NPC_MAX_KWS_IN_KEY];
1162 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1163 u64 action;
1164 u64 vtag_action;
1165 };
1166
1167 struct npc_mcam_write_entry_req {
1168 struct mbox_msghdr hdr;
1169 struct mcam_entry entry_data;
1170 u16 entry; /* MCAM entry to write this match key */
1171 u16 cntr; /* Counter for this MCAM entry */
1172 u8 intf; /* Rx or Tx interface */
1173 u8 enable_entry;/* Enable this MCAM entry ? */
1174 u8 set_cntr; /* Set counter for this entry ? */
1175 };
1176
1177 /* Enable/Disable a given entry */
1178 struct npc_mcam_ena_dis_entry_req {
1179 struct mbox_msghdr hdr;
1180 u16 entry;
1181 };
1182
1183 struct npc_mcam_shift_entry_req {
1184 struct mbox_msghdr hdr;
1185 #define NPC_MCAM_MAX_SHIFTS 64
1186 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1187 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1188 u16 shift_count; /* Number of entries to shift */
1189 };
1190
1191 struct npc_mcam_shift_entry_rsp {
1192 struct mbox_msghdr hdr;
1193 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1194 };
1195
1196 struct npc_mcam_alloc_counter_req {
1197 struct mbox_msghdr hdr;
1198 u8 contig; /* Contiguous counters ? */
1199 #define NPC_MAX_NONCONTIG_COUNTERS 64
1200 u16 count; /* Number of counters requested */
1201 };
1202
1203 struct npc_mcam_alloc_counter_rsp {
1204 struct mbox_msghdr hdr;
1205 u16 cntr; /* Counter allocated or start index if contiguous.
1206 * Invalid incase of non-contiguous.
1207 */
1208 u16 count; /* Number of counters allocated */
1209 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1210 };
1211
1212 struct npc_mcam_oper_counter_req {
1213 struct mbox_msghdr hdr;
1214 u16 cntr; /* Free a counter or clear/fetch it's stats */
1215 };
1216
1217 struct npc_mcam_oper_counter_rsp {
1218 struct mbox_msghdr hdr;
1219 u64 stat; /* valid only while fetching counter's stats */
1220 };
1221
1222 struct npc_mcam_unmap_counter_req {
1223 struct mbox_msghdr hdr;
1224 u16 cntr;
1225 u16 entry; /* Entry and counter to be unmapped */
1226 u8 all; /* Unmap all entries using this counter ? */
1227 };
1228
1229 struct npc_mcam_alloc_and_write_entry_req {
1230 struct mbox_msghdr hdr;
1231 struct mcam_entry entry_data;
1232 u16 ref_entry;
1233 u8 priority; /* Lower or higher w.r.t ref_entry */
1234 u8 intf; /* Rx or Tx interface */
1235 u8 enable_entry;/* Enable this MCAM entry ? */
1236 u8 alloc_cntr; /* Allocate counter and map ? */
1237 };
1238
1239 struct npc_mcam_alloc_and_write_entry_rsp {
1240 struct mbox_msghdr hdr;
1241 u16 entry;
1242 u16 cntr;
1243 };
1244
1245 struct npc_get_kex_cfg_rsp {
1246 struct mbox_msghdr hdr;
1247 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1248 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1249 #define NPC_MAX_INTF 2
1250 #define NPC_MAX_LID 8
1251 #define NPC_MAX_LT 16
1252 #define NPC_MAX_LD 2
1253 #define NPC_MAX_LFL 16
1254 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1255 u64 kex_ld_flags[NPC_MAX_LD];
1256 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1257 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1258 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1259 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1260 #define MKEX_NAME_LEN 128
1261 u8 mkex_pfl_name[MKEX_NAME_LEN];
1262 };
1263
1264 struct flow_msg {
1265 unsigned char dmac[6];
1266 unsigned char smac[6];
1267 __be16 etype;
1268 __be16 vlan_etype;
1269 __be16 vlan_tci;
1270 union {
1271 __be32 ip4src;
1272 __be32 ip6src[4];
1273 };
1274 union {
1275 __be32 ip4dst;
1276 __be32 ip6dst[4];
1277 };
1278 u8 tos;
1279 u8 ip_ver;
1280 u8 ip_proto;
1281 u8 tc;
1282 __be16 sport;
1283 __be16 dport;
1284 };
1285
1286 struct npc_install_flow_req {
1287 struct mbox_msghdr hdr;
1288 struct flow_msg packet;
1289 struct flow_msg mask;
1290 u64 features;
1291 u16 entry;
1292 u16 channel;
1293 u16 chan_mask;
1294 u8 intf;
1295 u8 set_cntr; /* If counter is available set counter for this entry ? */
1296 u8 default_rule;
1297 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1298 u16 vf;
1299 /* action */
1300 u32 index;
1301 u16 match_id;
1302 u8 flow_key_alg;
1303 u8 op;
1304 /* vtag rx action */
1305 u8 vtag0_type;
1306 u8 vtag0_valid;
1307 u8 vtag1_type;
1308 u8 vtag1_valid;
1309 /* vtag tx action */
1310 u16 vtag0_def;
1311 u8 vtag0_op;
1312 u16 vtag1_def;
1313 u8 vtag1_op;
1314 };
1315
1316 struct npc_install_flow_rsp {
1317 struct mbox_msghdr hdr;
1318 int counter; /* negative if no counter else counter number */
1319 };
1320
1321 struct npc_delete_flow_req {
1322 struct mbox_msghdr hdr;
1323 u16 entry;
1324 u16 start;/*Disable range of entries */
1325 u16 end;
1326 u8 all; /* PF + VFs */
1327 };
1328
1329 struct npc_mcam_read_entry_req {
1330 struct mbox_msghdr hdr;
1331 u16 entry; /* MCAM entry to read */
1332 };
1333
1334 struct npc_mcam_read_entry_rsp {
1335 struct mbox_msghdr hdr;
1336 struct mcam_entry entry_data;
1337 u8 intf;
1338 u8 enable;
1339 };
1340
1341 struct npc_mcam_read_base_rule_rsp {
1342 struct mbox_msghdr hdr;
1343 struct mcam_entry entry;
1344 };
1345
1346 struct npc_mcam_get_stats_req {
1347 struct mbox_msghdr hdr;
1348 u16 entry; /* mcam entry */
1349 };
1350
1351 struct npc_mcam_get_stats_rsp {
1352 struct mbox_msghdr hdr;
1353 u64 stat; /* counter stats */
1354 u8 stat_ena; /* enabled */
1355 };
1356
1357 enum ptp_op {
1358 PTP_OP_ADJFINE = 0,
1359 PTP_OP_GET_CLOCK = 1,
1360 };
1361
1362 struct ptp_req {
1363 struct mbox_msghdr hdr;
1364 u8 op;
1365 s64 scaled_ppm;
1366 };
1367
1368 struct ptp_rsp {
1369 struct mbox_msghdr hdr;
1370 u64 clk;
1371 };
1372
1373 struct set_vf_perm {
1374 struct mbox_msghdr hdr;
1375 u16 vf;
1376 #define RESET_VF_PERM BIT_ULL(0)
1377 #define VF_TRUSTED BIT_ULL(1)
1378 u64 flags;
1379 };
1380
1381 struct lmtst_tbl_setup_req {
1382 struct mbox_msghdr hdr;
1383 u64 dis_sched_early_comp :1;
1384 u64 sch_ena :1;
1385 u64 dis_line_pref :1;
1386 u64 ssow_pf_func :13;
1387 u16 base_pcifunc;
1388 u8 use_local_lmt_region;
1389 u64 lmt_iova;
1390 u64 rsvd[4];
1391 };
1392
1393 /* CPT mailbox error codes
1394 * Range 901 - 1000.
1395 */
1396 enum cpt_af_status {
1397 CPT_AF_ERR_PARAM = -901,
1398 CPT_AF_ERR_GRP_INVALID = -902,
1399 CPT_AF_ERR_LF_INVALID = -903,
1400 CPT_AF_ERR_ACCESS_DENIED = -904,
1401 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1402 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906
1403 };
1404
1405 /* CPT mbox message formats */
1406 struct cpt_rd_wr_reg_msg {
1407 struct mbox_msghdr hdr;
1408 u64 reg_offset;
1409 u64 *ret_val;
1410 u64 val;
1411 u8 is_write;
1412 int blkaddr;
1413 };
1414
1415 struct cpt_lf_alloc_req_msg {
1416 struct mbox_msghdr hdr;
1417 u16 nix_pf_func;
1418 u16 sso_pf_func;
1419 u16 eng_grpmsk;
1420 int blkaddr;
1421 };
1422
1423 /* Mailbox message request and response format for CPT stats. */
1424 struct cpt_sts_req {
1425 struct mbox_msghdr hdr;
1426 u8 blkaddr;
1427 };
1428
1429 struct cpt_sts_rsp {
1430 struct mbox_msghdr hdr;
1431 u64 inst_req_pc;
1432 u64 inst_lat_pc;
1433 u64 rd_req_pc;
1434 u64 rd_lat_pc;
1435 u64 rd_uc_pc;
1436 u64 active_cycles_pc;
1437 u64 ctx_mis_pc;
1438 u64 ctx_hit_pc;
1439 u64 ctx_aop_pc;
1440 u64 ctx_aop_lat_pc;
1441 u64 ctx_ifetch_pc;
1442 u64 ctx_ifetch_lat_pc;
1443 u64 ctx_ffetch_pc;
1444 u64 ctx_ffetch_lat_pc;
1445 u64 ctx_wback_pc;
1446 u64 ctx_wback_lat_pc;
1447 u64 ctx_psh_pc;
1448 u64 ctx_psh_lat_pc;
1449 u64 ctx_err;
1450 u64 ctx_enc_id;
1451 u64 ctx_flush_timer;
1452 u64 rxc_time;
1453 u64 rxc_time_cfg;
1454 u64 rxc_active_sts;
1455 u64 rxc_zombie_sts;
1456 u64 busy_sts_ae;
1457 u64 free_sts_ae;
1458 u64 busy_sts_se;
1459 u64 free_sts_se;
1460 u64 busy_sts_ie;
1461 u64 free_sts_ie;
1462 u64 exe_err_info;
1463 u64 cptclk_cnt;
1464 u64 diag;
1465 u64 rxc_dfrg;
1466 u64 x2p_link_cfg0;
1467 u64 x2p_link_cfg1;
1468 };
1469
1470 /* Mailbox message request format to configure reassembly timeout. */
1471 struct cpt_rxc_time_cfg_req {
1472 struct mbox_msghdr hdr;
1473 int blkaddr;
1474 u32 step;
1475 u16 zombie_thres;
1476 u16 zombie_limit;
1477 u16 active_thres;
1478 u16 active_limit;
1479 };
1480
1481 struct sdp_node_info {
1482 /* Node to which this PF belons to */
1483 u8 node_id;
1484 u8 max_vfs;
1485 u8 num_pf_rings;
1486 u8 pf_srn;
1487 #define SDP_MAX_VFS 128
1488 u8 vf_rings[SDP_MAX_VFS];
1489 };
1490
1491 struct sdp_chan_info_msg {
1492 struct mbox_msghdr hdr;
1493 struct sdp_node_info info;
1494 };
1495
1496 struct sdp_get_chan_info_msg {
1497 struct mbox_msghdr hdr;
1498 u16 chan_base;
1499 u16 num_chan;
1500 };
1501
1502 /* CGX mailbox error codes
1503 * Range 1101 - 1200.
1504 */
1505 enum cgx_af_status {
1506 LMAC_AF_ERR_INVALID_PARAM = -1101,
1507 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1508 LMAC_AF_ERR_PERM_DENIED = -1103,
1509 };
1510
1511 #endif /* MBOX_H */
1512
