Home
last modified time | relevance | path

Searched refs:pll3 (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/drivers/clk/sunxi/
DMakefile18 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o
/Linux-v5.15/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h211 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
Dintel_dpll_mgr.c1921 temp |= pll->state.hw_state.pll3; in bxt_ddi_pll_enable()
2046 hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2047 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
2211 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
2259 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_ddi_pll_get_freq()
2319 hw_state->pll3, in bxt_dump_hw_state()
Dintel_display.c8751 PIPE_CONF_CHECK_X(dpll_hw_state.pll3); in intel_pipe_config_compare()
/Linux-v5.15/drivers/gpu/drm/tegra/
Dsor.c368 unsigned int pll3; member
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2294 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2512 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2521 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
3294 .pll3 = 0x1a,
3466 .pll3 = 0x1a,
3527 .pll3 = 0x166,
[all …]
/Linux-v5.15/drivers/clk/qcom/
Dgcc-msm8960.c28 static struct clk_pll pll3 = { variable
3142 [PLL3] = &pll3.clkr,
3370 [PLL3] = &pll3.clkr,
Dgcc-ipq806x.c55 static struct clk_pll pll3 = { variable
2758 [PLL3] = &pll3.clkr,
/Linux-v5.15/arch/arm/boot/dts/
Dsh73a0.dtsi652 "pll3", "dsi0phy", "dsi1phy",