Searched refs:pll1_div (Results 1 – 4 of 4) sorted by relevance
26 static unsigned int pll1_div; variable43 unsigned long rate = clk->parent->rate / pll1_div; in pll_recalc()139 pll1_div = 3; in arch_clk_init()141 pll1_div = 4; in arch_clk_init()143 pll1_div = 1; in arch_clk_init()
65 u8 pll1_div; member
44 u8 pll1_div; member283 div = cpg_pll_config->pll1_div; in rcar_r8a779a0_cpg_clk_register()
458 div = cpg_pll_config->pll1_div; in rcar_gen3_cpg_clk_register()
