Searched refs:performance (Results 1 – 25 of 588) sorted by relevance
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80 if (ppc >= pr->performance->state_count || in acpi_processor_get_platform_limit()85 pr->performance->states[ppc].core_frequency * 1000); in acpi_processor_get_platform_limit()113 if (ignore_ppc || !pr->performance) { in acpi_processor_ppc_has_changed()143 if (!pr || !pr->performance || !pr->performance->state_count) in acpi_processor_get_bios_limit()145 *limit = pr->performance->states[pr->performance_platform_limit]. in acpi_processor_get_bios_limit()224 memcpy(&pr->performance->control_register, obj.buffer.pointer, in acpi_processor_get_performance_control()241 memcpy(&pr->performance->status_register, obj.buffer.pointer, in acpi_processor_get_performance_control()312 pr->performance->state_count = pss->package.count; in acpi_processor_get_performance_states()313 pr->performance->states = in acpi_processor_get_performance_states()317 if (!pr->performance->states) { in acpi_processor_get_performance_states()[all …]
11 performance of a logical processor on a contiguous and abstract performance12 scale. CPPC exposes a set of registers to describe abstract performance scale,13 to request performance levels and to measure per-cpu delivered performance.38 * highest_perf : Highest performance of this processor (abstract scale).39 * nominal_perf : Highest sustained performance of this processor41 * lowest_nonlinear_perf : Lowest performance of this processor with nonlinear43 * lowest_perf : Lowest performance of this processor (abstract scale).47 The above frequencies should only be used to report processor performance in51 * feedback_ctrs : Includes both Reference and delivered performance counter.52 Reference counter ticks up proportional to processor's reference performance.[all …]
5 tristate "Intel uncore performance events"9 Include support for Intel uncore performance events. These are13 tristate "Intel/AMD rapl performance events"17 Include support for Intel and AMD rapl performance events for power21 tristate "Intel cstate performance events"25 Include support for Intel cstate performance events for power38 tristate "AMD Uncore performance events"42 Include support for AMD uncore performance events for use with
8 collection of features that give more granular control over CPU performance.9 With Intel(R) SST, one server can be configured for power and performance for a15 …tel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enhancing-performance.pdf25 how these commands change the power and performance profile of the system under83 performance requirements. This helps users during deployment as they do not have86 that allows multiple optimized performance profiles per system. Each profile89 performance profile and meet CPU online/offline requirement, the user can expect93 Number or performance levels96 There can be multiple performance profiles on a system. To get the number of111 On this system under test, there are 4 performance profiles in addition to the[all …]
26 a value of 0 corresponds to a hint preference for highest performance31 with one of the strings: "performance", "balance-performance", "normal",
17 :doc:`CPU performance scaling subsystem <cpufreq>` in the Linux kernel25 than just an operating frequency or an operating performance point (see the30 uses frequencies for identifying operating performance points of CPUs and58 active mode, it uses its own internal performance scaling governor algorithm or59 allows the hardware to do performance scaling by itself, while in the passive61 a certain performance scaling algorithm. Which of them will be in effect88 active mode: ``powersave`` and ``performance``. The way they both operate94 Namely, if that option is set, the ``performance`` algorithm will be used by117 HWP + ``performance``123 internal P-state selection logic is expected to focus entirely on performance.[all …]
13 and performance14 balanced-performance Balance between performance and low16 towards performance17 performance High performance operation
7 performance impact notification (FPIN) event.15 performance impact notification (FPIN) event.23 performance impact notification (FPIN) event.
11 the power consumed by devices at various performance levels, and the kernel68 'performance domain' in the system. A performance domain is a group of CPUs69 whose performance is scaled together. Performance domains generally have a70 1-to-1 mapping with CPUFreq policies. All CPUs in a performance domain are71 required to have the same micro-architecture. CPUs in different performance84 2.2 Registration of performance domains87 Drivers are expected to register performance domains into the EM framework by94 for each performance state. The callback function provided by the driver is free97 performance domains using cpumask. For other devices than CPUs the last107 2.3 Accessing performance domains[all …]
14 depends on the nature of data that perf_events performance monitoring15 units (PMU) [2]_ and Perf collect and expose for performance analysis.16 Collected system and performance data may be split into several21 its topology, used kernel and Perf versions, performance monitoring30 faults, CPU migrations), architectural hardware performance counters46 So, perf_events performance monitoring and observability operations are56 all kernel security permission checks so perf_events performance70 as privileged processes with respect to perf_events performance73 privilege [13]_ (POSIX 1003.1e: 2.2.2.39) for performance monitoring and75 performance monitoring and observability in the system.[all …]
5 On modern systems the platform performance, temperature, fan and other13 operation or towards performance.19 NOT a goal of this API to allow monitoring the resulting performance20 characteristics. Monitoring performance is best done with device/vendor23 Specifically when selecting a high performance profile the actual achieved24 performance may be limited by various factors such as: the heat generated28 performance level.
7 - Identify worst case performance loss when doing dynamic frequency12 - Identify cpufreq related performance regressions between kernels18 - Power saving related regressions (In fact as better the performance28 For that purpose, it compares the performance governor to a configured56 takes on this machine and needs to be run in a loop using the performance58 Then the above test runs are processed using the performance governor61 on full performance and you get the overall performance loss.80 trigger of the cpufreq-bench, you will see no performance loss (compare with84 will always see 50% loads and you get worst performance impact never
145 dst_states = kcalloc(_pr->performance->state_count, in xen_copy_pss_data()150 dst_perf->state_count = _pr->performance->state_count; in xen_copy_pss_data()151 for (i = 0; i < _pr->performance->state_count; i++) { in xen_copy_pss_data()153 memcpy(&(dst_states[i]), &(_pr->performance->states[i]), in xen_copy_pss_data()169 dst->shared_type = _pr->performance->shared_type; in xen_copy_psd_data()171 pdomain = &(_pr->performance->domain_info); in xen_copy_psd_data()220 xen_copy_pct_data(&(_pr->performance->control_register), in push_pxx_to_hypervisor()222 xen_copy_pct_data(&(_pr->performance->status_register), in push_pxx_to_hypervisor()247 perf = _pr->performance; in push_pxx_to_hypervisor()280 if (_pr->performance && _pr->performance->states) in upload_pm_data()[all …]
6 Support for HiSilicon SoC L3 Cache performance monitor, Hydra Home7 Agent performance monitor and DDR Controller performance monitor.
53 System call performance (throughput).56 Memory access performance.76 Suite for evaluating performance of scheduler and IPC mechanisms.146 Suite for evaluating performance of core system call throughput (both usecs/op and ops/sec metrics).154 Suite for evaluating performance of simple memory copy in various ways.178 Suite for evaluating performance of simple memory set in various ways.234 Suite for evaluating perf's event synthesis performance.
23 a performance counter profile of guest os in realtime26 'perf kvm record <command>' to record the performance counter profile39 'perf kvm report' to display the performance counter profile information42 'perf kvm diff' to displays the performance difference amongst two perf.data51 'perf kvm stat <command>' to run a command and gather performance counter77 Collect host side performance profile.79 Collect guest side performance profile.
27 tristate "performance tests for RCU"36 This option provides a kernel module that runs performance40 Say Y here if you want RCU performance tests to be built into42 Say M if you want the RCU performance tests to build as a module.74 This option provides a kernel module that runs performance tests79 Say Y here if you want these performance tests built into the kernel.126 lifetime and kills performance. Don't try this on large
56 Say y if you want to use CPU performance monitors on ARM-based76 Provides support for performance monitor unit in ARM DynamIQ Shared85 Provides support for the DDR performance monitor in i.MX8, which94 Provides support for the L2 cache performance monitor unit (PMU)104 Provides support for the L3 cache performance monitor unit (PMU)123 Say y if you want to use APM X-Gene SoC performance monitors.
38 performance [inst/s]48 while still getting 'good' performance. It is essentially an alternative49 optimization objective to the current performance-only objective for the51 performance.78 task/CPU is, and to take this into consideration when evaluating performance vs84 per 'performance domain' in the system (see Documentation/power/energy-model.rst85 for futher details about performance domains).89 scheduler maintains a singly linked list of all performance domains intersecting95 necessarily match those of performance domains, the lists of different root99 Let us consider a platform with 12 CPUs, split in 3 performance domains[all …]
166 u16 performance; member206 u8 performance:1; member230 struct acpi_processor_performance *performance; member251 __percpu *performance);254 *performance, unsigned int cpu);
24 with lots of processors that may show reduced performance if30 250 Hz is a good compromise choice allowing server performance38 300 Hz is a good compromise choice allowing server performance
63 significant performance improvement on certain platforms(SGI Altix,67 (IA64, Xeon) resulting in noticeable performance improvement(up to 7%123 good performance::133 Transmit performance:164 Receive performance:173 b. Use 2-buffer mode. This results in large performance boost on
9 as CPU cache coherence, but may have different performance. For example,13 under different domains, or "nodes", based on locality and performance35 performance when accessing a given memory target. Each initiator-target55 nodes' access characteristics share the same performance relative to other69 be allocated from based on the node's performance characteristics. If79 The performance characteristics the kernel provides for the local initiators104 performance characteristics in order to provide large address space of130 attributes in order to maximize the performance out of such a setup.
15 sacrifice some performance due to increased latency19 the controller to have performance be a priority
