Searched refs:parent1 (Results 1 – 2 of 2) sorted by relevance
| /Linux-v5.15/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_28nm.c | 522 char clk_name[32], parent1[32], parent2[32], vco_name[32]; in pll_28nm_register() local
547 snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); in pll_28nm_register()
549 parent1, CLK_SET_RATE_PARENT, in pll_28nm_register()
557 snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->phy->id); in pll_28nm_register()
559 parent1, CLK_SET_RATE_PARENT, in pll_28nm_register()
565 snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); in pll_28nm_register()
567 parent1, 0, pll_28nm->phy->pll_base + in pll_28nm_register()
575 snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->phy->id); in pll_28nm_register()
579 parent1, parent2 in pll_28nm_register()
586 snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->phy->id); in pll_28nm_register()
[all …]
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| /Linux-v5.15/drivers/clk/davinci/ |
| D | da8xx-cfgchip.c | 198 const char *parent1; member
241 const char * const parent_names[] = { info->parent0, info->parent1 }; in da8xx_cfgchip_mux_clk_register()
271 .parent1 = "div4.5",
293 .parent1 = "pll1_sysclk2",
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