Searched refs:num_vcn_inst (Results 1 – 9 of 9) sorted by relevance
79 adev->vcn.num_vcn_inst = 2; in vcn_v2_5_early_init()85 adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS; in vcn_v2_5_early_init()86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()119 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()149 if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) { in vcn_v2_5_sw_init()162 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()240 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_sw_fini()275 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()326 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()394 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_mc_resume()[all …]
93 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; in vcn_v3_0_early_init()101 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; in vcn_v3_0_early_init()102 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_early_init()113 adev->vcn.num_vcn_inst = 1; in vcn_v3_0_early_init()154 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { in vcn_v3_0_sw_init()180 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_init()279 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_fini()323 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()352 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()396 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_fini()[all …]
86 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in amdgpu_vcn_sw_init()226 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_sw_init()261 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_sw_fini()320 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_suspend()347 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_resume()392 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_idle_work_handler()
303 adev->vcn.num_vcn_inst++; in amdgpu_discovery_reg_base_init()412 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { in amdgpu_discovery_harvest_ip()
236 uint8_t num_vcn_inst; member
475 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()487 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
69 adev->vcn.num_vcn_inst = 1; in vcn_v1_0_early_init()
71 adev->vcn.num_vcn_inst = 1; in vcn_v2_0_early_init()
768 if (adev->vcn.num_vcn_inst > 1) { in sienna_cichlid_set_default_dpm_table()807 if (adev->vcn.num_vcn_inst > 1) { in sienna_cichlid_set_default_dpm_table()913 if (adev->vcn.num_vcn_inst > 1) { in sienna_cichlid_dpm_set_vcn_enable()925 if (adev->vcn.num_vcn_inst > 1) { in sienna_cichlid_dpm_set_vcn_enable()
