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Searched refs:mmUVD_CGC_CTRL (Results 1 – 19 of 19) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c677 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
716 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
771 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
774 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
780 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
783 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
848 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
Duvd_v3_1.c213 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
229 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v3_1_set_dcm()
607 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
610 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
616 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
619 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
Duvd_v4_2.c612 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
615 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
621 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
624 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
635 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
651 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
Duvd_v6_0.c1343 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1383 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating()
1440 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1443 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1449 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1452 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1522 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
Dvcn_v1_0.c461 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
469 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
494 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
515 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
585 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
592 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
594 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
615 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
673 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_0.c491 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
498 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
523 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
544 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
621 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
651 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
658 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
660 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
681 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
Dvcn_v2_5.c555 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
562 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
590 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
611 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
689 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
720 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
727 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
729 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
749 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
Dvcn_v3_0.c717 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
724 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
752 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
773 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
873 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
901 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
908 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
910 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
931 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
Duvd_v7_0.c868 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
981 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
1618 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1664 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h34 #define mmUVD_CGC_CTRL 0x3D2C macro
Duvd_4_2_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_3_1_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_5_0_d.h50 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_6_0_d.h66 #define mmUVD_CGC_CTRL 0x3d2c macro
Duvd_7_0_offset.h146 #define mmUVD_CGC_CTRL … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h308 #define mmUVD_CGC_CTRL … macro
Dvcn_2_5_offset.h501 #define mmUVD_CGC_CTRL … macro
Dvcn_2_0_0_offset.h508 #define mmUVD_CGC_CTRL … macro
Dvcn_3_0_0_offset.h817 #define mmUVD_CGC_CTRL … macro