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Searched refs:mmSDMA0_F32_CNTL (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dsdma_v2_4.c395 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
400 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
976 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
978 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
983 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
985 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
Dcik_sdma.c417 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in cik_sdma_enable()
422 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); in cik_sdma_enable()
1083 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_soft_reset()
1085 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
1089 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset()
1091 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
Dsdma_v5_2.c582 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_enable()
584 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable()
715 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_gfx_resume()
717 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); in sdma_v5_2_gfx_resume()
Dsdma_v5_0.c700 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_enable()
702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable()
839 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_gfx_resume()
841 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); in sdma_v5_0_gfx_resume()
Dsdma_v4_0.c1139 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); in sdma_v4_0_enable()
1141 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); in sdma_v4_0_enable()
1511 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); in sdma_v4_0_start()
1513 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); in sdma_v4_0_start()
Dsdma_v3_0.c630 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v3_0_enable()
635 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_enable()
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h96 #define mmSDMA0_F32_CNTL … macro
Dsdma0_4_0_offset.h98 #define mmSDMA0_F32_CNTL 0x002a macro
Dsdma0_4_2_2_offset.h98 #define mmSDMA0_F32_CNTL … macro
Dsdma0_4_2_offset.h98 #define mmSDMA0_F32_CNTL … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h174 #define mmSDMA0_F32_CNTL 0x3412 macro
Doss_3_0_1_d.h172 #define mmSDMA0_F32_CNTL 0x3412 macro
Doss_2_0_d.h237 #define mmSDMA0_F32_CNTL 0x3412 macro
Doss_3_0_d.h309 #define mmSDMA0_F32_CNTL 0x3412 macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h73 #define mmSDMA0_F32_CNTL … macro
Dgc_10_3_0_offset.h78 #define mmSDMA0_F32_CNTL … macro