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Searched refs:mmSDMA0_CNTL (Results 1 – 16 of 16) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c379 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in cik_ctx_switch_enable()
394 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in cik_ctx_switch_enable()
1125 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1127 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1130 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1132 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1141 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1143 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1146 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1148 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
Dsdma_v2_4.c1020 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1022 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1025 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1027 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1036 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1038 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1041 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1043 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
Dsdma_v3_0.c588 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
607 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_ctx_switch_enable()
1354 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1356 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1359 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1361 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1370 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1372 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1375 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1377 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
Dsdma_v4_0.c1094 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); in sdma_v4_0_ctx_switch_enable()
1102 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); in sdma_v4_0_ctx_switch_enable()
1350 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_update_power_gating()
1354 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_update_power_gating()
1357 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_update_power_gating()
1360 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_update_power_gating()
1375 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); in sdma_v4_1_init_power_gating()
1378 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); in sdma_v4_1_init_power_gating()
1505 temp = RREG32_SDMA(i, mmSDMA0_CNTL); in sdma_v4_0_start()
1507 WREG32_SDMA(i, mmSDMA0_CNTL, temp); in sdma_v4_0_start()
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Dsdma_v5_0.c659 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_ctx_switch_enable()
673 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_0_ctx_switch_enable()
816 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_gfx_resume()
821 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); in sdma_v5_0_gfx_resume()
1508 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : in sdma_v5_0_set_trap_irq_state()
1509 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); in sdma_v5_0_set_trap_irq_state()
Dsdma_v5_2.c547 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_ctx_switch_enable()
558 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_2_ctx_switch_enable()
691 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_gfx_resume()
696 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); in sdma_v5_2_gfx_resume()
1459 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); in sdma_v5_2_set_trap_irq_state()
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h68 #define mmSDMA0_CNTL … macro
Dsdma0_4_0_offset.h70 #define mmSDMA0_CNTL 0x001c macro
Dsdma0_4_2_2_offset.h70 #define mmSDMA0_CNTL … macro
Dsdma0_4_2_offset.h70 #define mmSDMA0_CNTL … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h161 #define mmSDMA0_CNTL 0x3404 macro
Doss_3_0_1_d.h158 #define mmSDMA0_CNTL 0x3404 macro
Doss_2_0_d.h223 #define mmSDMA0_CNTL 0x3404 macro
Doss_3_0_d.h295 #define mmSDMA0_CNTL 0x3404 macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h45 #define mmSDMA0_CNTL … macro
Dgc_10_3_0_offset.h50 #define mmSDMA0_CNTL … macro