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Searched refs:mmSCRATCH_REG1_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_offset.h216 #define mmSCRATCH_REG1_BASE_IDX … macro
Dgc_9_0_offset.h4644 #define mmSCRATCH_REG1_BASE_IDX … macro
Dgc_9_1_offset.h4874 #define mmSCRATCH_REG1_BASE_IDX … macro
Dgc_9_2_1_offset.h4830 #define mmSCRATCH_REG1_BASE_IDX … macro
Dgc_10_1_0_offset.h7108 #define mmSCRATCH_REG1_BASE_IDX … macro
Dgc_10_3_0_offset.h6733 #define mmSCRATCH_REG1_BASE_IDX … macro
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c748 …scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()
749 …scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()
750 …scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()
Dgfx_v10_0.c1534 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; in gfx_v10_rlcg_rw()
1538 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; in gfx_v10_rlcg_rw()