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Searched refs:mmRLC_PG_CNTL (Results 1 – 14 of 14) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c3734 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3740 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3748 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3754 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3761 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
3767 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_cp_pg()
3774 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
3780 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gds_pg()
3797 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3800 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_cgpg()
[all …]
Dgfx_v9_0.c2946 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2951 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_up()
2960 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2965 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_sck_slow_down_on_power_down()
2974 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_cp_power_gating()
2979 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_cp_power_gating()
2987 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_cg_power_gating()
2992 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_cg_power_gating()
3000 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); in gfx_v9_0_enable_gfx_pipeline_powergating()
3005 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); in gfx_v9_0_enable_gfx_pipeline_powergating()
[all …]
Dgfx_v6_0.c2687 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_cp_pg()
2693 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_cp_pg()
2797 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_static_mgpg()
2803 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_static_mgpg()
2811 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v6_0_enable_gfx_dynamic_mgpg()
2817 WREG32(mmRLC_PG_CNTL, data); in gfx_v6_0_enable_gfx_dynamic_mgpg()
Dgfx_v10_0.c5366 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_0_rlc_smu_handshake_cntl()
5380 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); in gfx_v10_0_rlc_smu_handshake_cntl()
5460 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); in gfx_v10_0_rlc_resume()
8318 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); in gfx_v10_cntl_power_gating()
8325 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); in gfx_v10_cntl_power_gating()
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1165 #define mmRLC_PG_CNTL 0x30D7 macro
Dgfx_7_0_d.h1275 #define mmRLC_PG_CNTL 0x3103 macro
Dgfx_7_2_d.h1288 #define mmRLC_PG_CNTL 0x3103 macro
Dgfx_8_0_d.h1386 #define mmRLC_PG_CNTL 0xec43 macro
Dgfx_8_1_d.h1388 #define mmRLC_PG_CNTL 0xec43 macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6037 #define mmRLC_PG_CNTL … macro
Dgc_9_1_offset.h6259 #define mmRLC_PG_CNTL … macro
Dgc_9_2_1_offset.h6235 #define mmRLC_PG_CNTL … macro
Dgc_10_1_0_offset.h9357 #define mmRLC_PG_CNTL … macro
Dgc_10_3_0_offset.h9187 #define mmRLC_PG_CNTL … macro