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Searched refs:mmPHYPLLA_PIXCLK_RESYNC_CNTL (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h117 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
Ddcn_3_0_1_offset.h200 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
Ddcn_2_1_0_offset.h152 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
Ddcn_1_0_offset.h464 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
Ddcn_3_0_2_offset.h132 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
Ddcn_2_0_0_offset.h132 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
Ddcn_3_0_0_offset.h113 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_11_2_d.h1069 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x100 macro
Ddce_12_0_offset.h650 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … macro