Home
last modified time | relevance | path

Searched refs:mmMMSCH_VF_MAILBOX_RESP (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dmmsch_v2_0.h67 #define mmMMSCH_VF_MAILBOX_RESP … macro
Dvcn_v2_0.c1810 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_0_start_mmsch()
1827 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_0_start_mmsch()
1831 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_0_start_mmsch()
Dvcn_v2_5.c1131 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_5_mmsch_start()
1139 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1143 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
Dvcn_v3_0.c1479 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v3_0_start_sriov()
1491 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v3_0_start_sriov()
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_offset.h37 #define mmMMSCH_VF_MAILBOX_RESP … macro
Dvcn_3_0_0_offset.h65 #define mmMMSCH_VF_MAILBOX_RESP … macro