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Searched refs:mmGCMC_VM_MX_L1_TLB_CNTL (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v2_0.c191 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_init_tlb_regs()
203 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_init_tlb_regs()
372 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_0_gart_disable()
376 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_0_gart_disable()
Dgfxhub_v2_1.c192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_init_tlb_regs()
204 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_1_init_tlb_regs()
393 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); in gfxhub_v2_1_gart_disable()
397 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v2_1_gart_disable()
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h3739 #define mmGCMC_VM_MX_L1_TLB_CNTL … macro
Dgc_10_3_0_offset.h3686 #define mmGCMC_VM_MX_L1_TLB_CNTL … macro