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Searched refs:mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_offset.h10014 #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
Ddcn_3_0_2_offset.h11356 #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
Ddcn_2_0_0_offset.h12701 #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
Ddcn_3_0_0_offset.h12499 #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX … macro