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Searched refs:mmDP0_DP_DPHY_BS_SR_SWAP_CNTL (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c89 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC macro
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c88 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC macro
/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c94 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_11_0_d.h4557 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc macro
Ddce_11_2_d.h5789 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc macro
Ddce_12_0_offset.h10298 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h5048 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
Ddcn_3_0_1_offset.h8018 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
Ddcn_2_1_0_offset.h9951 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
Ddcn_1_0_offset.h8447 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
Ddcn_3_0_2_offset.h9630 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
Ddcn_2_0_0_offset.h11044 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro
Ddcn_3_0_0_offset.h10765 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … macro