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Searched refs:mmDC_HPD1_INT_CONTROL (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c265 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_set_polarity()
270 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_set_polarity()
306 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
308 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
2894 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); in dce_v6_0_set_hpd_interrupt_state()
2896 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); in dce_v6_0_set_hpd_interrupt_state()
2899 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); in dce_v6_0_set_hpd_interrupt_state()
2901 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); in dce_v6_0_set_hpd_interrupt_state()
3088 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_irq()
3090 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_irq()
Ddce_v8_0.c259 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v8_0_hpd_set_polarity()
264 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v8_0_hpd_set_polarity()
300 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v8_0_hpd_init()
302 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v8_0_hpd_init()
2986 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); in dce_v8_0_set_hpd_interrupt_state()
2988 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); in dce_v8_0_set_hpd_interrupt_state()
2991 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); in dce_v8_0_set_hpd_interrupt_state()
2993 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); in dce_v8_0_set_hpd_interrupt_state()
3180 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v8_0_hpd_irq()
3182 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v8_0_hpd_irq()
/Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h1283 #define mmDC_HPD1_INT_CONTROL 0x1808 macro
Ddce_8_0_d.h3513 #define mmDC_HPD1_INT_CONTROL 0x1808 macro