Searched refs:mmCP_RB0_WPTR (Results 1 – 15 of 15) sorted by relevance
| /Linux-v5.15/drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 2117 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v6_0_cp_gfx_resume()
2150 return RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_get_wptr()
2163 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v6_0_ring_set_wptr_gfx()
2164 (void)RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_set_wptr_gfx()
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| D | gfx_v7_0.c | 2631 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_cp_gfx_resume()
2666 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2673 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_ring_set_wptr_gfx()
2674 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
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| D | gfx_v8_0.c | 4306 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_cp_gfx_resume()
6061 return RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_get_wptr_gfx()
6073 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_gfx()
6074 (void)RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_set_wptr_gfx()
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| D | gfx_v9_0.c | 3337 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_cp_gfx_resume()
5285 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v9_0_ring_get_wptr_gfx()
5301 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_ring_set_wptr_gfx()
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| D | gfx_v10_0.c | 6395 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
8508 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v10_0_ring_get_wptr_gfx()
8524 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_ring_set_wptr_gfx()
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| /Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_6_0_d.h | 499 #define mmCP_RB0_WPTR 0x3045 macro
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| D | gfx_7_0_d.h | 214 #define mmCP_RB0_WPTR 0x3045 macro
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| D | gfx_7_2_d.h | 214 #define mmCP_RB0_WPTR 0x3045 macro
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| D | gfx_8_0_d.h | 238 #define mmCP_RB0_WPTR 0x3045 macro
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| D | gfx_8_1_d.h | 239 #define mmCP_RB0_WPTR 0x3045 macro
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| /Linux-v5.15/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 2420 #define mmCP_RB0_WPTR … macro
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| D | gc_9_1_offset.h | 2697 #define mmCP_RB0_WPTR … macro
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| D | gc_9_2_1_offset.h | 2635 #define mmCP_RB0_WPTR … macro
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| D | gc_10_1_0_offset.h | 4761 #define mmCP_RB0_WPTR … macro
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| D | gc_10_3_0_offset.h | 4408 #define mmCP_RB0_WPTR … macro
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