1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
68 	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
69 	MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
70 	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
71 };
72 
73 enum {
74 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
75 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
76 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
77 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
78 };
79 
80 enum {
81 	MLX5_SHARED_RESOURCE_UID = 0xffff,
82 };
83 
84 enum {
85 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
86 };
87 
88 enum {
89 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
90 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
91 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
92 };
93 
94 enum {
95 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
96 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
97 	MLX5_OBJ_TYPE_MKEY = 0xff01,
98 	MLX5_OBJ_TYPE_QP = 0xff02,
99 	MLX5_OBJ_TYPE_PSV = 0xff03,
100 	MLX5_OBJ_TYPE_RMP = 0xff04,
101 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
102 	MLX5_OBJ_TYPE_RQ = 0xff06,
103 	MLX5_OBJ_TYPE_SQ = 0xff07,
104 	MLX5_OBJ_TYPE_TIR = 0xff08,
105 	MLX5_OBJ_TYPE_TIS = 0xff09,
106 	MLX5_OBJ_TYPE_DCT = 0xff0a,
107 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
108 	MLX5_OBJ_TYPE_RQT = 0xff0e,
109 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
110 	MLX5_OBJ_TYPE_CQ = 0xff10,
111 };
112 
113 enum {
114 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
115 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
116 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
117 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
118 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
119 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
120 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
121 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
122 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
123 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
124 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
125 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
126 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
127 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
128 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
129 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
130 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
131 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
132 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
133 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
134 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
135 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
136 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
137 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
138 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
139 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
140 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
141 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
142 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
143 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
144 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
145 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
146 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
147 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
148 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
149 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
150 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
151 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
152 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
153 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
154 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
155 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
156 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
157 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
158 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
159 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
160 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
161 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
162 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
163 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
164 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
165 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
166 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
167 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
168 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
169 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
170 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
171 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
172 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
173 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
174 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
175 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
176 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
177 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
178 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
179 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
180 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
181 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
182 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
183 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
184 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
185 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
186 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
187 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
188 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
189 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
190 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
191 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
192 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
193 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
194 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
195 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
196 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
197 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
198 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
199 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
200 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
201 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
202 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
203 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
204 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
205 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
206 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
207 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
208 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
209 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
210 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
211 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
212 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
213 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
214 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
215 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
216 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
217 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
218 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
219 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
220 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
221 	MLX5_CMD_OP_NOP                           = 0x80d,
222 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
223 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
224 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
225 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
226 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
227 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
228 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
229 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
230 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
231 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
232 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
233 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
234 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
235 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
236 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
237 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
238 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
239 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
240 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
241 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
242 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
243 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
244 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
245 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
246 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
247 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
248 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
249 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
250 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
251 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
252 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
253 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
254 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
255 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
256 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
257 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
258 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
259 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
260 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
261 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
262 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
263 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
264 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
265 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
266 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
267 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
268 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
269 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
270 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
271 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
272 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
273 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
274 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
275 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
276 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
277 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
278 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
279 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
280 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
281 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
282 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
283 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
284 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
285 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
286 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
287 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
288 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
289 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
290 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
291 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
292 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
293 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
294 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
295 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
296 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
297 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
298 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
299 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
300 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
301 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
302 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
303 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
304 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
305 	MLX5_CMD_OP_MAX
306 };
307 
308 /* Valid range for general commands that don't work over an object */
309 enum {
310 	MLX5_CMD_OP_GENERAL_START = 0xb00,
311 	MLX5_CMD_OP_GENERAL_END = 0xd00,
312 };
313 
314 struct mlx5_ifc_flow_table_fields_supported_bits {
315 	u8         outer_dmac[0x1];
316 	u8         outer_smac[0x1];
317 	u8         outer_ether_type[0x1];
318 	u8         outer_ip_version[0x1];
319 	u8         outer_first_prio[0x1];
320 	u8         outer_first_cfi[0x1];
321 	u8         outer_first_vid[0x1];
322 	u8         outer_ipv4_ttl[0x1];
323 	u8         outer_second_prio[0x1];
324 	u8         outer_second_cfi[0x1];
325 	u8         outer_second_vid[0x1];
326 	u8         reserved_at_b[0x1];
327 	u8         outer_sip[0x1];
328 	u8         outer_dip[0x1];
329 	u8         outer_frag[0x1];
330 	u8         outer_ip_protocol[0x1];
331 	u8         outer_ip_ecn[0x1];
332 	u8         outer_ip_dscp[0x1];
333 	u8         outer_udp_sport[0x1];
334 	u8         outer_udp_dport[0x1];
335 	u8         outer_tcp_sport[0x1];
336 	u8         outer_tcp_dport[0x1];
337 	u8         outer_tcp_flags[0x1];
338 	u8         outer_gre_protocol[0x1];
339 	u8         outer_gre_key[0x1];
340 	u8         outer_vxlan_vni[0x1];
341 	u8         outer_geneve_vni[0x1];
342 	u8         outer_geneve_oam[0x1];
343 	u8         outer_geneve_protocol_type[0x1];
344 	u8         outer_geneve_opt_len[0x1];
345 	u8         reserved_at_1e[0x1];
346 	u8         source_eswitch_port[0x1];
347 
348 	u8         inner_dmac[0x1];
349 	u8         inner_smac[0x1];
350 	u8         inner_ether_type[0x1];
351 	u8         inner_ip_version[0x1];
352 	u8         inner_first_prio[0x1];
353 	u8         inner_first_cfi[0x1];
354 	u8         inner_first_vid[0x1];
355 	u8         reserved_at_27[0x1];
356 	u8         inner_second_prio[0x1];
357 	u8         inner_second_cfi[0x1];
358 	u8         inner_second_vid[0x1];
359 	u8         reserved_at_2b[0x1];
360 	u8         inner_sip[0x1];
361 	u8         inner_dip[0x1];
362 	u8         inner_frag[0x1];
363 	u8         inner_ip_protocol[0x1];
364 	u8         inner_ip_ecn[0x1];
365 	u8         inner_ip_dscp[0x1];
366 	u8         inner_udp_sport[0x1];
367 	u8         inner_udp_dport[0x1];
368 	u8         inner_tcp_sport[0x1];
369 	u8         inner_tcp_dport[0x1];
370 	u8         inner_tcp_flags[0x1];
371 	u8         reserved_at_37[0x9];
372 
373 	u8         geneve_tlv_option_0_data[0x1];
374 	u8         reserved_at_41[0x4];
375 	u8         outer_first_mpls_over_udp[0x4];
376 	u8         outer_first_mpls_over_gre[0x4];
377 	u8         inner_first_mpls[0x4];
378 	u8         outer_first_mpls[0x4];
379 	u8         reserved_at_55[0x2];
380 	u8	   outer_esp_spi[0x1];
381 	u8         reserved_at_58[0x2];
382 	u8         bth_dst_qp[0x1];
383 	u8         reserved_at_5b[0x5];
384 
385 	u8         reserved_at_60[0x18];
386 	u8         metadata_reg_c_7[0x1];
387 	u8         metadata_reg_c_6[0x1];
388 	u8         metadata_reg_c_5[0x1];
389 	u8         metadata_reg_c_4[0x1];
390 	u8         metadata_reg_c_3[0x1];
391 	u8         metadata_reg_c_2[0x1];
392 	u8         metadata_reg_c_1[0x1];
393 	u8         metadata_reg_c_0[0x1];
394 };
395 
396 struct mlx5_ifc_flow_table_prop_layout_bits {
397 	u8         ft_support[0x1];
398 	u8         reserved_at_1[0x1];
399 	u8         flow_counter[0x1];
400 	u8	   flow_modify_en[0x1];
401 	u8         modify_root[0x1];
402 	u8         identified_miss_table_mode[0x1];
403 	u8         flow_table_modify[0x1];
404 	u8         reformat[0x1];
405 	u8         decap[0x1];
406 	u8         reserved_at_9[0x1];
407 	u8         pop_vlan[0x1];
408 	u8         push_vlan[0x1];
409 	u8         reserved_at_c[0x1];
410 	u8         pop_vlan_2[0x1];
411 	u8         push_vlan_2[0x1];
412 	u8	   reformat_and_vlan_action[0x1];
413 	u8	   reserved_at_10[0x1];
414 	u8         sw_owner[0x1];
415 	u8	   reformat_l3_tunnel_to_l2[0x1];
416 	u8	   reformat_l2_to_l3_tunnel[0x1];
417 	u8	   reformat_and_modify_action[0x1];
418 	u8	   ignore_flow_level[0x1];
419 	u8         reserved_at_16[0x1];
420 	u8	   table_miss_action_domain[0x1];
421 	u8         termination_table[0x1];
422 	u8         reformat_and_fwd_to_table[0x1];
423 	u8         reserved_at_1a[0x2];
424 	u8         ipsec_encrypt[0x1];
425 	u8         ipsec_decrypt[0x1];
426 	u8         sw_owner_v2[0x1];
427 	u8         reserved_at_1f[0x1];
428 
429 	u8         termination_table_raw_traffic[0x1];
430 	u8         reserved_at_21[0x1];
431 	u8         log_max_ft_size[0x6];
432 	u8         log_max_modify_header_context[0x8];
433 	u8         max_modify_header_actions[0x8];
434 	u8         max_ft_level[0x8];
435 
436 	u8         reserved_at_40[0x20];
437 
438 	u8         reserved_at_60[0x2];
439 	u8         reformat_insert[0x1];
440 	u8         reformat_remove[0x1];
441 	u8         reserver_at_64[0x14];
442 	u8         log_max_ft_num[0x8];
443 
444 	u8         reserved_at_80[0x10];
445 	u8         log_max_flow_counter[0x8];
446 	u8         log_max_destination[0x8];
447 
448 	u8         reserved_at_a0[0x18];
449 	u8         log_max_flow[0x8];
450 
451 	u8         reserved_at_c0[0x40];
452 
453 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
454 
455 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
456 };
457 
458 struct mlx5_ifc_odp_per_transport_service_cap_bits {
459 	u8         send[0x1];
460 	u8         receive[0x1];
461 	u8         write[0x1];
462 	u8         read[0x1];
463 	u8         atomic[0x1];
464 	u8         srq_receive[0x1];
465 	u8         reserved_at_6[0x1a];
466 };
467 
468 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
469 	u8         smac_47_16[0x20];
470 
471 	u8         smac_15_0[0x10];
472 	u8         ethertype[0x10];
473 
474 	u8         dmac_47_16[0x20];
475 
476 	u8         dmac_15_0[0x10];
477 	u8         first_prio[0x3];
478 	u8         first_cfi[0x1];
479 	u8         first_vid[0xc];
480 
481 	u8         ip_protocol[0x8];
482 	u8         ip_dscp[0x6];
483 	u8         ip_ecn[0x2];
484 	u8         cvlan_tag[0x1];
485 	u8         svlan_tag[0x1];
486 	u8         frag[0x1];
487 	u8         ip_version[0x4];
488 	u8         tcp_flags[0x9];
489 
490 	u8         tcp_sport[0x10];
491 	u8         tcp_dport[0x10];
492 
493 	u8         reserved_at_c0[0x18];
494 	u8         ttl_hoplimit[0x8];
495 
496 	u8         udp_sport[0x10];
497 	u8         udp_dport[0x10];
498 
499 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
500 
501 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
502 };
503 
504 struct mlx5_ifc_nvgre_key_bits {
505 	u8 hi[0x18];
506 	u8 lo[0x8];
507 };
508 
509 union mlx5_ifc_gre_key_bits {
510 	struct mlx5_ifc_nvgre_key_bits nvgre;
511 	u8 key[0x20];
512 };
513 
514 struct mlx5_ifc_fte_match_set_misc_bits {
515 	u8         gre_c_present[0x1];
516 	u8         reserved_at_1[0x1];
517 	u8         gre_k_present[0x1];
518 	u8         gre_s_present[0x1];
519 	u8         source_vhca_port[0x4];
520 	u8         source_sqn[0x18];
521 
522 	u8         source_eswitch_owner_vhca_id[0x10];
523 	u8         source_port[0x10];
524 
525 	u8         outer_second_prio[0x3];
526 	u8         outer_second_cfi[0x1];
527 	u8         outer_second_vid[0xc];
528 	u8         inner_second_prio[0x3];
529 	u8         inner_second_cfi[0x1];
530 	u8         inner_second_vid[0xc];
531 
532 	u8         outer_second_cvlan_tag[0x1];
533 	u8         inner_second_cvlan_tag[0x1];
534 	u8         outer_second_svlan_tag[0x1];
535 	u8         inner_second_svlan_tag[0x1];
536 	u8         reserved_at_64[0xc];
537 	u8         gre_protocol[0x10];
538 
539 	union mlx5_ifc_gre_key_bits gre_key;
540 
541 	u8         vxlan_vni[0x18];
542 	u8         reserved_at_b8[0x8];
543 
544 	u8         geneve_vni[0x18];
545 	u8         reserved_at_d8[0x7];
546 	u8         geneve_oam[0x1];
547 
548 	u8         reserved_at_e0[0xc];
549 	u8         outer_ipv6_flow_label[0x14];
550 
551 	u8         reserved_at_100[0xc];
552 	u8         inner_ipv6_flow_label[0x14];
553 
554 	u8         reserved_at_120[0xa];
555 	u8         geneve_opt_len[0x6];
556 	u8         geneve_protocol_type[0x10];
557 
558 	u8         reserved_at_140[0x8];
559 	u8         bth_dst_qp[0x18];
560 	u8	   reserved_at_160[0x20];
561 	u8	   outer_esp_spi[0x20];
562 	u8         reserved_at_1a0[0x60];
563 };
564 
565 struct mlx5_ifc_fte_match_mpls_bits {
566 	u8         mpls_label[0x14];
567 	u8         mpls_exp[0x3];
568 	u8         mpls_s_bos[0x1];
569 	u8         mpls_ttl[0x8];
570 };
571 
572 struct mlx5_ifc_fte_match_set_misc2_bits {
573 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
574 
575 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
576 
577 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
578 
579 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
580 
581 	u8         metadata_reg_c_7[0x20];
582 
583 	u8         metadata_reg_c_6[0x20];
584 
585 	u8         metadata_reg_c_5[0x20];
586 
587 	u8         metadata_reg_c_4[0x20];
588 
589 	u8         metadata_reg_c_3[0x20];
590 
591 	u8         metadata_reg_c_2[0x20];
592 
593 	u8         metadata_reg_c_1[0x20];
594 
595 	u8         metadata_reg_c_0[0x20];
596 
597 	u8         metadata_reg_a[0x20];
598 
599 	u8         reserved_at_1a0[0x60];
600 };
601 
602 struct mlx5_ifc_fte_match_set_misc3_bits {
603 	u8         inner_tcp_seq_num[0x20];
604 
605 	u8         outer_tcp_seq_num[0x20];
606 
607 	u8         inner_tcp_ack_num[0x20];
608 
609 	u8         outer_tcp_ack_num[0x20];
610 
611 	u8	   reserved_at_80[0x8];
612 	u8         outer_vxlan_gpe_vni[0x18];
613 
614 	u8         outer_vxlan_gpe_next_protocol[0x8];
615 	u8         outer_vxlan_gpe_flags[0x8];
616 	u8	   reserved_at_b0[0x10];
617 
618 	u8	   icmp_header_data[0x20];
619 
620 	u8	   icmpv6_header_data[0x20];
621 
622 	u8	   icmp_type[0x8];
623 	u8	   icmp_code[0x8];
624 	u8	   icmpv6_type[0x8];
625 	u8	   icmpv6_code[0x8];
626 
627 	u8         geneve_tlv_option_0_data[0x20];
628 
629 	u8	   gtpu_teid[0x20];
630 
631 	u8	   gtpu_msg_type[0x8];
632 	u8	   gtpu_msg_flags[0x8];
633 	u8	   reserved_at_170[0x10];
634 
635 	u8	   gtpu_dw_2[0x20];
636 
637 	u8	   gtpu_first_ext_dw_0[0x20];
638 
639 	u8	   gtpu_dw_0[0x20];
640 
641 	u8	   reserved_at_1e0[0x20];
642 };
643 
644 struct mlx5_ifc_fte_match_set_misc4_bits {
645 	u8         prog_sample_field_value_0[0x20];
646 
647 	u8         prog_sample_field_id_0[0x20];
648 
649 	u8         prog_sample_field_value_1[0x20];
650 
651 	u8         prog_sample_field_id_1[0x20];
652 
653 	u8         prog_sample_field_value_2[0x20];
654 
655 	u8         prog_sample_field_id_2[0x20];
656 
657 	u8         prog_sample_field_value_3[0x20];
658 
659 	u8         prog_sample_field_id_3[0x20];
660 
661 	u8         reserved_at_100[0x100];
662 };
663 
664 struct mlx5_ifc_cmd_pas_bits {
665 	u8         pa_h[0x20];
666 
667 	u8         pa_l[0x14];
668 	u8         reserved_at_34[0xc];
669 };
670 
671 struct mlx5_ifc_uint64_bits {
672 	u8         hi[0x20];
673 
674 	u8         lo[0x20];
675 };
676 
677 enum {
678 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
679 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
680 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
681 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
682 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
683 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
684 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
685 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
686 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
687 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
688 };
689 
690 struct mlx5_ifc_ads_bits {
691 	u8         fl[0x1];
692 	u8         free_ar[0x1];
693 	u8         reserved_at_2[0xe];
694 	u8         pkey_index[0x10];
695 
696 	u8         reserved_at_20[0x8];
697 	u8         grh[0x1];
698 	u8         mlid[0x7];
699 	u8         rlid[0x10];
700 
701 	u8         ack_timeout[0x5];
702 	u8         reserved_at_45[0x3];
703 	u8         src_addr_index[0x8];
704 	u8         reserved_at_50[0x4];
705 	u8         stat_rate[0x4];
706 	u8         hop_limit[0x8];
707 
708 	u8         reserved_at_60[0x4];
709 	u8         tclass[0x8];
710 	u8         flow_label[0x14];
711 
712 	u8         rgid_rip[16][0x8];
713 
714 	u8         reserved_at_100[0x4];
715 	u8         f_dscp[0x1];
716 	u8         f_ecn[0x1];
717 	u8         reserved_at_106[0x1];
718 	u8         f_eth_prio[0x1];
719 	u8         ecn[0x2];
720 	u8         dscp[0x6];
721 	u8         udp_sport[0x10];
722 
723 	u8         dei_cfi[0x1];
724 	u8         eth_prio[0x3];
725 	u8         sl[0x4];
726 	u8         vhca_port_num[0x8];
727 	u8         rmac_47_32[0x10];
728 
729 	u8         rmac_31_0[0x20];
730 };
731 
732 struct mlx5_ifc_flow_table_nic_cap_bits {
733 	u8         nic_rx_multi_path_tirs[0x1];
734 	u8         nic_rx_multi_path_tirs_fts[0x1];
735 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
736 	u8	   reserved_at_3[0x4];
737 	u8	   sw_owner_reformat_supported[0x1];
738 	u8	   reserved_at_8[0x18];
739 
740 	u8	   encap_general_header[0x1];
741 	u8	   reserved_at_21[0xa];
742 	u8	   log_max_packet_reformat_context[0x5];
743 	u8	   reserved_at_30[0x6];
744 	u8	   max_encap_header_size[0xa];
745 	u8	   reserved_at_40[0x1c0];
746 
747 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
748 
749 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
750 
751 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
752 
753 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
754 
755 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
756 
757 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
758 
759 	u8         reserved_at_e00[0x1200];
760 
761 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
762 
763 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
764 
765 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
766 
767 	u8         reserved_at_20c0[0x5f40];
768 };
769 
770 enum {
771 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
772 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
773 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
774 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
775 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
776 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
777 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
778 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
779 };
780 
781 struct mlx5_ifc_flow_table_eswitch_cap_bits {
782 	u8      fdb_to_vport_reg_c_id[0x8];
783 	u8      reserved_at_8[0xd];
784 	u8      fdb_modify_header_fwd_to_table[0x1];
785 	u8      reserved_at_16[0x1];
786 	u8      flow_source[0x1];
787 	u8      reserved_at_18[0x2];
788 	u8      multi_fdb_encap[0x1];
789 	u8      egress_acl_forward_to_vport[0x1];
790 	u8      fdb_multi_path_to_table[0x1];
791 	u8      reserved_at_1d[0x3];
792 
793 	u8      reserved_at_20[0x1e0];
794 
795 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
796 
797 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
798 
799 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
800 
801 	u8      reserved_at_800[0x1000];
802 
803 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
804 
805 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
806 
807 	u8      sw_steering_uplink_icm_address_rx[0x40];
808 
809 	u8      sw_steering_uplink_icm_address_tx[0x40];
810 
811 	u8      reserved_at_1900[0x6700];
812 };
813 
814 enum {
815 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
816 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
817 };
818 
819 struct mlx5_ifc_e_switch_cap_bits {
820 	u8         vport_svlan_strip[0x1];
821 	u8         vport_cvlan_strip[0x1];
822 	u8         vport_svlan_insert[0x1];
823 	u8         vport_cvlan_insert_if_not_exist[0x1];
824 	u8         vport_cvlan_insert_overwrite[0x1];
825 	u8         reserved_at_5[0x2];
826 	u8         esw_shared_ingress_acl[0x1];
827 	u8         esw_uplink_ingress_acl[0x1];
828 	u8         root_ft_on_other_esw[0x1];
829 	u8         reserved_at_a[0xf];
830 	u8         esw_functions_changed[0x1];
831 	u8         reserved_at_1a[0x1];
832 	u8         ecpf_vport_exists[0x1];
833 	u8         counter_eswitch_affinity[0x1];
834 	u8         merged_eswitch[0x1];
835 	u8         nic_vport_node_guid_modify[0x1];
836 	u8         nic_vport_port_guid_modify[0x1];
837 
838 	u8         vxlan_encap_decap[0x1];
839 	u8         nvgre_encap_decap[0x1];
840 	u8         reserved_at_22[0x1];
841 	u8         log_max_fdb_encap_uplink[0x5];
842 	u8         reserved_at_21[0x3];
843 	u8         log_max_packet_reformat_context[0x5];
844 	u8         reserved_2b[0x6];
845 	u8         max_encap_header_size[0xa];
846 
847 	u8         reserved_at_40[0xb];
848 	u8         log_max_esw_sf[0x5];
849 	u8         esw_sf_base_id[0x10];
850 
851 	u8         reserved_at_60[0x7a0];
852 
853 };
854 
855 struct mlx5_ifc_qos_cap_bits {
856 	u8         packet_pacing[0x1];
857 	u8         esw_scheduling[0x1];
858 	u8         esw_bw_share[0x1];
859 	u8         esw_rate_limit[0x1];
860 	u8         reserved_at_4[0x1];
861 	u8         packet_pacing_burst_bound[0x1];
862 	u8         packet_pacing_typical_size[0x1];
863 	u8         reserved_at_7[0x1];
864 	u8         nic_sq_scheduling[0x1];
865 	u8         nic_bw_share[0x1];
866 	u8         nic_rate_limit[0x1];
867 	u8         packet_pacing_uid[0x1];
868 	u8         log_esw_max_sched_depth[0x4];
869 	u8         reserved_at_10[0x10];
870 
871 	u8         reserved_at_20[0xb];
872 	u8         log_max_qos_nic_queue_group[0x5];
873 	u8         reserved_at_30[0x10];
874 
875 	u8         packet_pacing_max_rate[0x20];
876 
877 	u8         packet_pacing_min_rate[0x20];
878 
879 	u8         reserved_at_80[0x10];
880 	u8         packet_pacing_rate_table_size[0x10];
881 
882 	u8         esw_element_type[0x10];
883 	u8         esw_tsar_type[0x10];
884 
885 	u8         reserved_at_c0[0x10];
886 	u8         max_qos_para_vport[0x10];
887 
888 	u8         max_tsar_bw_share[0x20];
889 
890 	u8         reserved_at_100[0x700];
891 };
892 
893 struct mlx5_ifc_debug_cap_bits {
894 	u8         core_dump_general[0x1];
895 	u8         core_dump_qp[0x1];
896 	u8         reserved_at_2[0x7];
897 	u8         resource_dump[0x1];
898 	u8         reserved_at_a[0x16];
899 
900 	u8         reserved_at_20[0x2];
901 	u8         stall_detect[0x1];
902 	u8         reserved_at_23[0x1d];
903 
904 	u8         reserved_at_40[0x7c0];
905 };
906 
907 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
908 	u8         csum_cap[0x1];
909 	u8         vlan_cap[0x1];
910 	u8         lro_cap[0x1];
911 	u8         lro_psh_flag[0x1];
912 	u8         lro_time_stamp[0x1];
913 	u8         reserved_at_5[0x2];
914 	u8         wqe_vlan_insert[0x1];
915 	u8         self_lb_en_modifiable[0x1];
916 	u8         reserved_at_9[0x2];
917 	u8         max_lso_cap[0x5];
918 	u8         multi_pkt_send_wqe[0x2];
919 	u8	   wqe_inline_mode[0x2];
920 	u8         rss_ind_tbl_cap[0x4];
921 	u8         reg_umr_sq[0x1];
922 	u8         scatter_fcs[0x1];
923 	u8         enhanced_multi_pkt_send_wqe[0x1];
924 	u8         tunnel_lso_const_out_ip_id[0x1];
925 	u8         tunnel_lro_gre[0x1];
926 	u8         tunnel_lro_vxlan[0x1];
927 	u8         tunnel_stateless_gre[0x1];
928 	u8         tunnel_stateless_vxlan[0x1];
929 
930 	u8         swp[0x1];
931 	u8         swp_csum[0x1];
932 	u8         swp_lso[0x1];
933 	u8         cqe_checksum_full[0x1];
934 	u8         tunnel_stateless_geneve_tx[0x1];
935 	u8         tunnel_stateless_mpls_over_udp[0x1];
936 	u8         tunnel_stateless_mpls_over_gre[0x1];
937 	u8         tunnel_stateless_vxlan_gpe[0x1];
938 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
939 	u8         tunnel_stateless_ip_over_ip[0x1];
940 	u8         insert_trailer[0x1];
941 	u8         reserved_at_2b[0x1];
942 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
943 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
944 	u8         reserved_at_2e[0x2];
945 	u8         max_vxlan_udp_ports[0x8];
946 	u8         reserved_at_38[0x6];
947 	u8         max_geneve_opt_len[0x1];
948 	u8         tunnel_stateless_geneve_rx[0x1];
949 
950 	u8         reserved_at_40[0x10];
951 	u8         lro_min_mss_size[0x10];
952 
953 	u8         reserved_at_60[0x120];
954 
955 	u8         lro_timer_supported_periods[4][0x20];
956 
957 	u8         reserved_at_200[0x600];
958 };
959 
960 enum {
961 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
962 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
963 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
964 };
965 
966 struct mlx5_ifc_roce_cap_bits {
967 	u8         roce_apm[0x1];
968 	u8         reserved_at_1[0x3];
969 	u8         sw_r_roce_src_udp_port[0x1];
970 	u8         fl_rc_qp_when_roce_disabled[0x1];
971 	u8         fl_rc_qp_when_roce_enabled[0x1];
972 	u8         reserved_at_7[0x17];
973 	u8	   qp_ts_format[0x2];
974 
975 	u8         reserved_at_20[0x60];
976 
977 	u8         reserved_at_80[0xc];
978 	u8         l3_type[0x4];
979 	u8         reserved_at_90[0x8];
980 	u8         roce_version[0x8];
981 
982 	u8         reserved_at_a0[0x10];
983 	u8         r_roce_dest_udp_port[0x10];
984 
985 	u8         r_roce_max_src_udp_port[0x10];
986 	u8         r_roce_min_src_udp_port[0x10];
987 
988 	u8         reserved_at_e0[0x10];
989 	u8         roce_address_table_size[0x10];
990 
991 	u8         reserved_at_100[0x700];
992 };
993 
994 struct mlx5_ifc_sync_steering_in_bits {
995 	u8         opcode[0x10];
996 	u8         uid[0x10];
997 
998 	u8         reserved_at_20[0x10];
999 	u8         op_mod[0x10];
1000 
1001 	u8         reserved_at_40[0xc0];
1002 };
1003 
1004 struct mlx5_ifc_sync_steering_out_bits {
1005 	u8         status[0x8];
1006 	u8         reserved_at_8[0x18];
1007 
1008 	u8         syndrome[0x20];
1009 
1010 	u8         reserved_at_40[0x40];
1011 };
1012 
1013 struct mlx5_ifc_device_mem_cap_bits {
1014 	u8         memic[0x1];
1015 	u8         reserved_at_1[0x1f];
1016 
1017 	u8         reserved_at_20[0xb];
1018 	u8         log_min_memic_alloc_size[0x5];
1019 	u8         reserved_at_30[0x8];
1020 	u8	   log_max_memic_addr_alignment[0x8];
1021 
1022 	u8         memic_bar_start_addr[0x40];
1023 
1024 	u8         memic_bar_size[0x20];
1025 
1026 	u8         max_memic_size[0x20];
1027 
1028 	u8         steering_sw_icm_start_address[0x40];
1029 
1030 	u8         reserved_at_100[0x8];
1031 	u8         log_header_modify_sw_icm_size[0x8];
1032 	u8         reserved_at_110[0x2];
1033 	u8         log_sw_icm_alloc_granularity[0x6];
1034 	u8         log_steering_sw_icm_size[0x8];
1035 
1036 	u8         reserved_at_120[0x20];
1037 
1038 	u8         header_modify_sw_icm_start_address[0x40];
1039 
1040 	u8         reserved_at_180[0x80];
1041 
1042 	u8         memic_operations[0x20];
1043 
1044 	u8         reserved_at_220[0x5e0];
1045 };
1046 
1047 struct mlx5_ifc_device_event_cap_bits {
1048 	u8         user_affiliated_events[4][0x40];
1049 
1050 	u8         user_unaffiliated_events[4][0x40];
1051 };
1052 
1053 struct mlx5_ifc_virtio_emulation_cap_bits {
1054 	u8         desc_tunnel_offload_type[0x1];
1055 	u8         eth_frame_offload_type[0x1];
1056 	u8         virtio_version_1_0[0x1];
1057 	u8         device_features_bits_mask[0xd];
1058 	u8         event_mode[0x8];
1059 	u8         virtio_queue_type[0x8];
1060 
1061 	u8         max_tunnel_desc[0x10];
1062 	u8         reserved_at_30[0x3];
1063 	u8         log_doorbell_stride[0x5];
1064 	u8         reserved_at_38[0x3];
1065 	u8         log_doorbell_bar_size[0x5];
1066 
1067 	u8         doorbell_bar_offset[0x40];
1068 
1069 	u8         max_emulated_devices[0x8];
1070 	u8         max_num_virtio_queues[0x18];
1071 
1072 	u8         reserved_at_a0[0x60];
1073 
1074 	u8         umem_1_buffer_param_a[0x20];
1075 
1076 	u8         umem_1_buffer_param_b[0x20];
1077 
1078 	u8         umem_2_buffer_param_a[0x20];
1079 
1080 	u8         umem_2_buffer_param_b[0x20];
1081 
1082 	u8         umem_3_buffer_param_a[0x20];
1083 
1084 	u8         umem_3_buffer_param_b[0x20];
1085 
1086 	u8         reserved_at_1c0[0x640];
1087 };
1088 
1089 enum {
1090 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1091 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1092 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1093 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1094 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1095 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1096 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1097 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1098 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1099 };
1100 
1101 enum {
1102 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1103 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1104 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1105 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1106 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1107 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1108 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1109 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1110 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1111 };
1112 
1113 struct mlx5_ifc_atomic_caps_bits {
1114 	u8         reserved_at_0[0x40];
1115 
1116 	u8         atomic_req_8B_endianness_mode[0x2];
1117 	u8         reserved_at_42[0x4];
1118 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1119 
1120 	u8         reserved_at_47[0x19];
1121 
1122 	u8         reserved_at_60[0x20];
1123 
1124 	u8         reserved_at_80[0x10];
1125 	u8         atomic_operations[0x10];
1126 
1127 	u8         reserved_at_a0[0x10];
1128 	u8         atomic_size_qp[0x10];
1129 
1130 	u8         reserved_at_c0[0x10];
1131 	u8         atomic_size_dc[0x10];
1132 
1133 	u8         reserved_at_e0[0x720];
1134 };
1135 
1136 struct mlx5_ifc_odp_cap_bits {
1137 	u8         reserved_at_0[0x40];
1138 
1139 	u8         sig[0x1];
1140 	u8         reserved_at_41[0x1f];
1141 
1142 	u8         reserved_at_60[0x20];
1143 
1144 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1145 
1146 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1147 
1148 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1149 
1150 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1151 
1152 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1153 
1154 	u8         reserved_at_120[0x6E0];
1155 };
1156 
1157 struct mlx5_ifc_calc_op {
1158 	u8        reserved_at_0[0x10];
1159 	u8        reserved_at_10[0x9];
1160 	u8        op_swap_endianness[0x1];
1161 	u8        op_min[0x1];
1162 	u8        op_xor[0x1];
1163 	u8        op_or[0x1];
1164 	u8        op_and[0x1];
1165 	u8        op_max[0x1];
1166 	u8        op_add[0x1];
1167 };
1168 
1169 struct mlx5_ifc_vector_calc_cap_bits {
1170 	u8         calc_matrix[0x1];
1171 	u8         reserved_at_1[0x1f];
1172 	u8         reserved_at_20[0x8];
1173 	u8         max_vec_count[0x8];
1174 	u8         reserved_at_30[0xd];
1175 	u8         max_chunk_size[0x3];
1176 	struct mlx5_ifc_calc_op calc0;
1177 	struct mlx5_ifc_calc_op calc1;
1178 	struct mlx5_ifc_calc_op calc2;
1179 	struct mlx5_ifc_calc_op calc3;
1180 
1181 	u8         reserved_at_c0[0x720];
1182 };
1183 
1184 struct mlx5_ifc_tls_cap_bits {
1185 	u8         tls_1_2_aes_gcm_128[0x1];
1186 	u8         tls_1_3_aes_gcm_128[0x1];
1187 	u8         tls_1_2_aes_gcm_256[0x1];
1188 	u8         tls_1_3_aes_gcm_256[0x1];
1189 	u8         reserved_at_4[0x1c];
1190 
1191 	u8         reserved_at_20[0x7e0];
1192 };
1193 
1194 struct mlx5_ifc_ipsec_cap_bits {
1195 	u8         ipsec_full_offload[0x1];
1196 	u8         ipsec_crypto_offload[0x1];
1197 	u8         ipsec_esn[0x1];
1198 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1199 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1200 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1201 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1202 	u8         reserved_at_7[0x4];
1203 	u8         log_max_ipsec_offload[0x5];
1204 	u8         reserved_at_10[0x10];
1205 
1206 	u8         min_log_ipsec_full_replay_window[0x8];
1207 	u8         max_log_ipsec_full_replay_window[0x8];
1208 	u8         reserved_at_30[0x7d0];
1209 };
1210 
1211 enum {
1212 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1213 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1214 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1215 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1216 };
1217 
1218 enum {
1219 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1220 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1221 };
1222 
1223 enum {
1224 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1225 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1226 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1227 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1228 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1229 };
1230 
1231 enum {
1232 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1233 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1234 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1235 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1236 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1237 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1238 };
1239 
1240 enum {
1241 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1242 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1243 };
1244 
1245 enum {
1246 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1247 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1248 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1249 };
1250 
1251 enum {
1252 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1253 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1254 };
1255 
1256 enum {
1257 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1258 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1259 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1260 };
1261 
1262 enum {
1263 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1264 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1265 	mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1266 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1267 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1268 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1269 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1270 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1271 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1272 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1273 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1274 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1275 };
1276 
1277 enum {
1278 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1279 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1280 };
1281 
1282 #define MLX5_FC_BULK_SIZE_FACTOR 128
1283 
1284 enum mlx5_fc_bulk_alloc_bitmask {
1285 	MLX5_FC_BULK_128   = (1 << 0),
1286 	MLX5_FC_BULK_256   = (1 << 1),
1287 	MLX5_FC_BULK_512   = (1 << 2),
1288 	MLX5_FC_BULK_1024  = (1 << 3),
1289 	MLX5_FC_BULK_2048  = (1 << 4),
1290 	MLX5_FC_BULK_4096  = (1 << 5),
1291 	MLX5_FC_BULK_8192  = (1 << 6),
1292 	MLX5_FC_BULK_16384 = (1 << 7),
1293 };
1294 
1295 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1296 
1297 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1298 
1299 enum {
1300 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1301 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1302 };
1303 
1304 struct mlx5_ifc_cmd_hca_cap_bits {
1305 	u8         reserved_at_0[0x1f];
1306 	u8         vhca_resource_manager[0x1];
1307 
1308 	u8         hca_cap_2[0x1];
1309 	u8         reserved_at_21[0x2];
1310 	u8         event_on_vhca_state_teardown_request[0x1];
1311 	u8         event_on_vhca_state_in_use[0x1];
1312 	u8         event_on_vhca_state_active[0x1];
1313 	u8         event_on_vhca_state_allocated[0x1];
1314 	u8         event_on_vhca_state_invalid[0x1];
1315 	u8         reserved_at_28[0x8];
1316 	u8         vhca_id[0x10];
1317 
1318 	u8         reserved_at_40[0x40];
1319 
1320 	u8         log_max_srq_sz[0x8];
1321 	u8         log_max_qp_sz[0x8];
1322 	u8         event_cap[0x1];
1323 	u8         reserved_at_91[0x2];
1324 	u8         isolate_vl_tc_new[0x1];
1325 	u8         reserved_at_94[0x4];
1326 	u8         prio_tag_required[0x1];
1327 	u8         reserved_at_99[0x2];
1328 	u8         log_max_qp[0x5];
1329 
1330 	u8         reserved_at_a0[0x3];
1331 	u8	   ece_support[0x1];
1332 	u8	   reserved_at_a4[0x5];
1333 	u8         reg_c_preserve[0x1];
1334 	u8         reserved_at_aa[0x1];
1335 	u8         log_max_srq[0x5];
1336 	u8         reserved_at_b0[0x1];
1337 	u8         uplink_follow[0x1];
1338 	u8         ts_cqe_to_dest_cqn[0x1];
1339 	u8         reserved_at_b3[0xd];
1340 
1341 	u8         max_sgl_for_optimized_performance[0x8];
1342 	u8         log_max_cq_sz[0x8];
1343 	u8         relaxed_ordering_write_umr[0x1];
1344 	u8         relaxed_ordering_read_umr[0x1];
1345 	u8         reserved_at_d2[0x7];
1346 	u8         virtio_net_device_emualtion_manager[0x1];
1347 	u8         virtio_blk_device_emualtion_manager[0x1];
1348 	u8         log_max_cq[0x5];
1349 
1350 	u8         log_max_eq_sz[0x8];
1351 	u8         relaxed_ordering_write[0x1];
1352 	u8         relaxed_ordering_read[0x1];
1353 	u8         log_max_mkey[0x6];
1354 	u8         reserved_at_f0[0x8];
1355 	u8         dump_fill_mkey[0x1];
1356 	u8         reserved_at_f9[0x2];
1357 	u8         fast_teardown[0x1];
1358 	u8         log_max_eq[0x4];
1359 
1360 	u8         max_indirection[0x8];
1361 	u8         fixed_buffer_size[0x1];
1362 	u8         log_max_mrw_sz[0x7];
1363 	u8         force_teardown[0x1];
1364 	u8         reserved_at_111[0x1];
1365 	u8         log_max_bsf_list_size[0x6];
1366 	u8         umr_extended_translation_offset[0x1];
1367 	u8         null_mkey[0x1];
1368 	u8         log_max_klm_list_size[0x6];
1369 
1370 	u8         reserved_at_120[0xa];
1371 	u8         log_max_ra_req_dc[0x6];
1372 	u8         reserved_at_130[0xa];
1373 	u8         log_max_ra_res_dc[0x6];
1374 
1375 	u8         reserved_at_140[0x6];
1376 	u8         release_all_pages[0x1];
1377 	u8         reserved_at_147[0x2];
1378 	u8         roce_accl[0x1];
1379 	u8         log_max_ra_req_qp[0x6];
1380 	u8         reserved_at_150[0xa];
1381 	u8         log_max_ra_res_qp[0x6];
1382 
1383 	u8         end_pad[0x1];
1384 	u8         cc_query_allowed[0x1];
1385 	u8         cc_modify_allowed[0x1];
1386 	u8         start_pad[0x1];
1387 	u8         cache_line_128byte[0x1];
1388 	u8         reserved_at_165[0x4];
1389 	u8         rts2rts_qp_counters_set_id[0x1];
1390 	u8         reserved_at_16a[0x2];
1391 	u8         vnic_env_int_rq_oob[0x1];
1392 	u8         sbcam_reg[0x1];
1393 	u8         reserved_at_16e[0x1];
1394 	u8         qcam_reg[0x1];
1395 	u8         gid_table_size[0x10];
1396 
1397 	u8         out_of_seq_cnt[0x1];
1398 	u8         vport_counters[0x1];
1399 	u8         retransmission_q_counters[0x1];
1400 	u8         debug[0x1];
1401 	u8         modify_rq_counter_set_id[0x1];
1402 	u8         rq_delay_drop[0x1];
1403 	u8         max_qp_cnt[0xa];
1404 	u8         pkey_table_size[0x10];
1405 
1406 	u8         vport_group_manager[0x1];
1407 	u8         vhca_group_manager[0x1];
1408 	u8         ib_virt[0x1];
1409 	u8         eth_virt[0x1];
1410 	u8         vnic_env_queue_counters[0x1];
1411 	u8         ets[0x1];
1412 	u8         nic_flow_table[0x1];
1413 	u8         eswitch_manager[0x1];
1414 	u8         device_memory[0x1];
1415 	u8         mcam_reg[0x1];
1416 	u8         pcam_reg[0x1];
1417 	u8         local_ca_ack_delay[0x5];
1418 	u8         port_module_event[0x1];
1419 	u8         enhanced_error_q_counters[0x1];
1420 	u8         ports_check[0x1];
1421 	u8         reserved_at_1b3[0x1];
1422 	u8         disable_link_up[0x1];
1423 	u8         beacon_led[0x1];
1424 	u8         port_type[0x2];
1425 	u8         num_ports[0x8];
1426 
1427 	u8         reserved_at_1c0[0x1];
1428 	u8         pps[0x1];
1429 	u8         pps_modify[0x1];
1430 	u8         log_max_msg[0x5];
1431 	u8         reserved_at_1c8[0x4];
1432 	u8         max_tc[0x4];
1433 	u8         temp_warn_event[0x1];
1434 	u8         dcbx[0x1];
1435 	u8         general_notification_event[0x1];
1436 	u8         reserved_at_1d3[0x2];
1437 	u8         fpga[0x1];
1438 	u8         rol_s[0x1];
1439 	u8         rol_g[0x1];
1440 	u8         reserved_at_1d8[0x1];
1441 	u8         wol_s[0x1];
1442 	u8         wol_g[0x1];
1443 	u8         wol_a[0x1];
1444 	u8         wol_b[0x1];
1445 	u8         wol_m[0x1];
1446 	u8         wol_u[0x1];
1447 	u8         wol_p[0x1];
1448 
1449 	u8         stat_rate_support[0x10];
1450 	u8         reserved_at_1f0[0x1];
1451 	u8         pci_sync_for_fw_update_event[0x1];
1452 	u8         reserved_at_1f2[0x6];
1453 	u8         init2_lag_tx_port_affinity[0x1];
1454 	u8         reserved_at_1fa[0x3];
1455 	u8         cqe_version[0x4];
1456 
1457 	u8         compact_address_vector[0x1];
1458 	u8         striding_rq[0x1];
1459 	u8         reserved_at_202[0x1];
1460 	u8         ipoib_enhanced_offloads[0x1];
1461 	u8         ipoib_basic_offloads[0x1];
1462 	u8         reserved_at_205[0x1];
1463 	u8         repeated_block_disabled[0x1];
1464 	u8         umr_modify_entity_size_disabled[0x1];
1465 	u8         umr_modify_atomic_disabled[0x1];
1466 	u8         umr_indirect_mkey_disabled[0x1];
1467 	u8         umr_fence[0x2];
1468 	u8         dc_req_scat_data_cqe[0x1];
1469 	u8         reserved_at_20d[0x2];
1470 	u8         drain_sigerr[0x1];
1471 	u8         cmdif_checksum[0x2];
1472 	u8         sigerr_cqe[0x1];
1473 	u8         reserved_at_213[0x1];
1474 	u8         wq_signature[0x1];
1475 	u8         sctr_data_cqe[0x1];
1476 	u8         reserved_at_216[0x1];
1477 	u8         sho[0x1];
1478 	u8         tph[0x1];
1479 	u8         rf[0x1];
1480 	u8         dct[0x1];
1481 	u8         qos[0x1];
1482 	u8         eth_net_offloads[0x1];
1483 	u8         roce[0x1];
1484 	u8         atomic[0x1];
1485 	u8         reserved_at_21f[0x1];
1486 
1487 	u8         cq_oi[0x1];
1488 	u8         cq_resize[0x1];
1489 	u8         cq_moderation[0x1];
1490 	u8         reserved_at_223[0x3];
1491 	u8         cq_eq_remap[0x1];
1492 	u8         pg[0x1];
1493 	u8         block_lb_mc[0x1];
1494 	u8         reserved_at_229[0x1];
1495 	u8         scqe_break_moderation[0x1];
1496 	u8         cq_period_start_from_cqe[0x1];
1497 	u8         cd[0x1];
1498 	u8         reserved_at_22d[0x1];
1499 	u8         apm[0x1];
1500 	u8         vector_calc[0x1];
1501 	u8         umr_ptr_rlky[0x1];
1502 	u8	   imaicl[0x1];
1503 	u8	   qp_packet_based[0x1];
1504 	u8         reserved_at_233[0x3];
1505 	u8         qkv[0x1];
1506 	u8         pkv[0x1];
1507 	u8         set_deth_sqpn[0x1];
1508 	u8         reserved_at_239[0x3];
1509 	u8         xrc[0x1];
1510 	u8         ud[0x1];
1511 	u8         uc[0x1];
1512 	u8         rc[0x1];
1513 
1514 	u8         uar_4k[0x1];
1515 	u8         reserved_at_241[0x9];
1516 	u8         uar_sz[0x6];
1517 	u8         reserved_at_248[0x2];
1518 	u8         umem_uid_0[0x1];
1519 	u8         reserved_at_250[0x5];
1520 	u8         log_pg_sz[0x8];
1521 
1522 	u8         bf[0x1];
1523 	u8         driver_version[0x1];
1524 	u8         pad_tx_eth_packet[0x1];
1525 	u8         reserved_at_263[0x3];
1526 	u8         mkey_by_name[0x1];
1527 	u8         reserved_at_267[0x4];
1528 
1529 	u8         log_bf_reg_size[0x5];
1530 
1531 	u8         reserved_at_270[0x6];
1532 	u8         lag_dct[0x2];
1533 	u8         lag_tx_port_affinity[0x1];
1534 	u8         lag_native_fdb_selection[0x1];
1535 	u8         reserved_at_27a[0x1];
1536 	u8         lag_master[0x1];
1537 	u8         num_lag_ports[0x4];
1538 
1539 	u8         reserved_at_280[0x10];
1540 	u8         max_wqe_sz_sq[0x10];
1541 
1542 	u8         reserved_at_2a0[0x10];
1543 	u8         max_wqe_sz_rq[0x10];
1544 
1545 	u8         max_flow_counter_31_16[0x10];
1546 	u8         max_wqe_sz_sq_dc[0x10];
1547 
1548 	u8         reserved_at_2e0[0x7];
1549 	u8         max_qp_mcg[0x19];
1550 
1551 	u8         reserved_at_300[0x10];
1552 	u8         flow_counter_bulk_alloc[0x8];
1553 	u8         log_max_mcg[0x8];
1554 
1555 	u8         reserved_at_320[0x3];
1556 	u8         log_max_transport_domain[0x5];
1557 	u8         reserved_at_328[0x3];
1558 	u8         log_max_pd[0x5];
1559 	u8         reserved_at_330[0xb];
1560 	u8         log_max_xrcd[0x5];
1561 
1562 	u8         nic_receive_steering_discard[0x1];
1563 	u8         receive_discard_vport_down[0x1];
1564 	u8         transmit_discard_vport_down[0x1];
1565 	u8         reserved_at_343[0x5];
1566 	u8         log_max_flow_counter_bulk[0x8];
1567 	u8         max_flow_counter_15_0[0x10];
1568 
1569 
1570 	u8         reserved_at_360[0x3];
1571 	u8         log_max_rq[0x5];
1572 	u8         reserved_at_368[0x3];
1573 	u8         log_max_sq[0x5];
1574 	u8         reserved_at_370[0x3];
1575 	u8         log_max_tir[0x5];
1576 	u8         reserved_at_378[0x3];
1577 	u8         log_max_tis[0x5];
1578 
1579 	u8         basic_cyclic_rcv_wqe[0x1];
1580 	u8         reserved_at_381[0x2];
1581 	u8         log_max_rmp[0x5];
1582 	u8         reserved_at_388[0x3];
1583 	u8         log_max_rqt[0x5];
1584 	u8         reserved_at_390[0x3];
1585 	u8         log_max_rqt_size[0x5];
1586 	u8         reserved_at_398[0x3];
1587 	u8         log_max_tis_per_sq[0x5];
1588 
1589 	u8         ext_stride_num_range[0x1];
1590 	u8         reserved_at_3a1[0x2];
1591 	u8         log_max_stride_sz_rq[0x5];
1592 	u8         reserved_at_3a8[0x3];
1593 	u8         log_min_stride_sz_rq[0x5];
1594 	u8         reserved_at_3b0[0x3];
1595 	u8         log_max_stride_sz_sq[0x5];
1596 	u8         reserved_at_3b8[0x3];
1597 	u8         log_min_stride_sz_sq[0x5];
1598 
1599 	u8         hairpin[0x1];
1600 	u8         reserved_at_3c1[0x2];
1601 	u8         log_max_hairpin_queues[0x5];
1602 	u8         reserved_at_3c8[0x3];
1603 	u8         log_max_hairpin_wq_data_sz[0x5];
1604 	u8         reserved_at_3d0[0x3];
1605 	u8         log_max_hairpin_num_packets[0x5];
1606 	u8         reserved_at_3d8[0x3];
1607 	u8         log_max_wq_sz[0x5];
1608 
1609 	u8         nic_vport_change_event[0x1];
1610 	u8         disable_local_lb_uc[0x1];
1611 	u8         disable_local_lb_mc[0x1];
1612 	u8         log_min_hairpin_wq_data_sz[0x5];
1613 	u8         reserved_at_3e8[0x2];
1614 	u8         vhca_state[0x1];
1615 	u8         log_max_vlan_list[0x5];
1616 	u8         reserved_at_3f0[0x3];
1617 	u8         log_max_current_mc_list[0x5];
1618 	u8         reserved_at_3f8[0x3];
1619 	u8         log_max_current_uc_list[0x5];
1620 
1621 	u8         general_obj_types[0x40];
1622 
1623 	u8         sq_ts_format[0x2];
1624 	u8         rq_ts_format[0x2];
1625 	u8         steering_format_version[0x4];
1626 	u8         create_qp_start_hint[0x18];
1627 
1628 	u8         reserved_at_460[0x3];
1629 	u8         log_max_uctx[0x5];
1630 	u8         reserved_at_468[0x2];
1631 	u8         ipsec_offload[0x1];
1632 	u8         log_max_umem[0x5];
1633 	u8         max_num_eqs[0x10];
1634 
1635 	u8         reserved_at_480[0x1];
1636 	u8         tls_tx[0x1];
1637 	u8         tls_rx[0x1];
1638 	u8         log_max_l2_table[0x5];
1639 	u8         reserved_at_488[0x8];
1640 	u8         log_uar_page_sz[0x10];
1641 
1642 	u8         reserved_at_4a0[0x20];
1643 	u8         device_frequency_mhz[0x20];
1644 	u8         device_frequency_khz[0x20];
1645 
1646 	u8         reserved_at_500[0x20];
1647 	u8	   num_of_uars_per_page[0x20];
1648 
1649 	u8         flex_parser_protocols[0x20];
1650 
1651 	u8         max_geneve_tlv_options[0x8];
1652 	u8         reserved_at_568[0x3];
1653 	u8         max_geneve_tlv_option_data_len[0x5];
1654 	u8         reserved_at_570[0x10];
1655 
1656 	u8	   reserved_at_580[0xb];
1657 	u8	   log_max_dci_stream_channels[0x5];
1658 	u8	   reserved_at_590[0x3];
1659 	u8	   log_max_dci_errored_streams[0x5];
1660 	u8	   reserved_at_598[0x8];
1661 
1662 	u8         reserved_at_5a0[0x13];
1663 	u8         log_max_dek[0x5];
1664 	u8         reserved_at_5b8[0x4];
1665 	u8         mini_cqe_resp_stride_index[0x1];
1666 	u8         cqe_128_always[0x1];
1667 	u8         cqe_compression_128[0x1];
1668 	u8         cqe_compression[0x1];
1669 
1670 	u8         cqe_compression_timeout[0x10];
1671 	u8         cqe_compression_max_num[0x10];
1672 
1673 	u8         reserved_at_5e0[0x8];
1674 	u8         flex_parser_id_gtpu_dw_0[0x4];
1675 	u8         reserved_at_5ec[0x4];
1676 	u8         tag_matching[0x1];
1677 	u8         rndv_offload_rc[0x1];
1678 	u8         rndv_offload_dc[0x1];
1679 	u8         log_tag_matching_list_sz[0x5];
1680 	u8         reserved_at_5f8[0x3];
1681 	u8         log_max_xrq[0x5];
1682 
1683 	u8	   affiliate_nic_vport_criteria[0x8];
1684 	u8	   native_port_num[0x8];
1685 	u8	   num_vhca_ports[0x8];
1686 	u8         flex_parser_id_gtpu_teid[0x4];
1687 	u8         reserved_at_61c[0x2];
1688 	u8	   sw_owner_id[0x1];
1689 	u8         reserved_at_61f[0x1];
1690 
1691 	u8         max_num_of_monitor_counters[0x10];
1692 	u8         num_ppcnt_monitor_counters[0x10];
1693 
1694 	u8         max_num_sf[0x10];
1695 	u8         num_q_monitor_counters[0x10];
1696 
1697 	u8         reserved_at_660[0x20];
1698 
1699 	u8         sf[0x1];
1700 	u8         sf_set_partition[0x1];
1701 	u8         reserved_at_682[0x1];
1702 	u8         log_max_sf[0x5];
1703 	u8         apu[0x1];
1704 	u8         reserved_at_689[0x7];
1705 	u8         log_min_sf_size[0x8];
1706 	u8         max_num_sf_partitions[0x8];
1707 
1708 	u8         uctx_cap[0x20];
1709 
1710 	u8         reserved_at_6c0[0x4];
1711 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
1712 	u8         flex_parser_id_icmp_dw1[0x4];
1713 	u8         flex_parser_id_icmp_dw0[0x4];
1714 	u8         flex_parser_id_icmpv6_dw1[0x4];
1715 	u8         flex_parser_id_icmpv6_dw0[0x4];
1716 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1717 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1718 
1719 	u8	   reserved_at_6e0[0x10];
1720 	u8	   sf_base_id[0x10];
1721 
1722 	u8         flex_parser_id_gtpu_dw_2[0x4];
1723 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1724 	u8	   num_total_dynamic_vf_msix[0x18];
1725 	u8	   reserved_at_720[0x14];
1726 	u8	   dynamic_msix_table_size[0xc];
1727 	u8	   reserved_at_740[0xc];
1728 	u8	   min_dynamic_vf_msix_table_size[0x4];
1729 	u8	   reserved_at_750[0x4];
1730 	u8	   max_dynamic_vf_msix_table_size[0xc];
1731 
1732 	u8	   reserved_at_760[0x20];
1733 	u8	   vhca_tunnel_commands[0x40];
1734 	u8	   reserved_at_7c0[0x40];
1735 };
1736 
1737 struct mlx5_ifc_cmd_hca_cap_2_bits {
1738 	u8	   reserved_at_0[0xa0];
1739 
1740 	u8	   max_reformat_insert_size[0x8];
1741 	u8	   max_reformat_insert_offset[0x8];
1742 	u8	   max_reformat_remove_size[0x8];
1743 	u8	   max_reformat_remove_offset[0x8];
1744 
1745 	u8	   reserved_at_c0[0x740];
1746 };
1747 
1748 enum mlx5_flow_destination_type {
1749 	MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1750 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1751 	MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1752 	MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1753 
1754 	MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1755 	MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1756 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1757 };
1758 
1759 enum mlx5_flow_table_miss_action {
1760 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1761 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1762 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1763 };
1764 
1765 struct mlx5_ifc_dest_format_struct_bits {
1766 	u8         destination_type[0x8];
1767 	u8         destination_id[0x18];
1768 
1769 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
1770 	u8         packet_reformat[0x1];
1771 	u8         reserved_at_22[0xe];
1772 	u8         destination_eswitch_owner_vhca_id[0x10];
1773 };
1774 
1775 struct mlx5_ifc_flow_counter_list_bits {
1776 	u8         flow_counter_id[0x20];
1777 
1778 	u8         reserved_at_20[0x20];
1779 };
1780 
1781 struct mlx5_ifc_extended_dest_format_bits {
1782 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
1783 
1784 	u8         packet_reformat_id[0x20];
1785 
1786 	u8         reserved_at_60[0x20];
1787 };
1788 
1789 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1790 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1791 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1792 };
1793 
1794 struct mlx5_ifc_fte_match_param_bits {
1795 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1796 
1797 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1798 
1799 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1800 
1801 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1802 
1803 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1804 
1805 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1806 
1807 	u8         reserved_at_c00[0x400];
1808 };
1809 
1810 enum {
1811 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1812 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1813 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1814 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1815 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1816 };
1817 
1818 struct mlx5_ifc_rx_hash_field_select_bits {
1819 	u8         l3_prot_type[0x1];
1820 	u8         l4_prot_type[0x1];
1821 	u8         selected_fields[0x1e];
1822 };
1823 
1824 enum {
1825 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1826 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1827 };
1828 
1829 enum {
1830 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1831 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1832 };
1833 
1834 struct mlx5_ifc_wq_bits {
1835 	u8         wq_type[0x4];
1836 	u8         wq_signature[0x1];
1837 	u8         end_padding_mode[0x2];
1838 	u8         cd_slave[0x1];
1839 	u8         reserved_at_8[0x18];
1840 
1841 	u8         hds_skip_first_sge[0x1];
1842 	u8         log2_hds_buf_size[0x3];
1843 	u8         reserved_at_24[0x7];
1844 	u8         page_offset[0x5];
1845 	u8         lwm[0x10];
1846 
1847 	u8         reserved_at_40[0x8];
1848 	u8         pd[0x18];
1849 
1850 	u8         reserved_at_60[0x8];
1851 	u8         uar_page[0x18];
1852 
1853 	u8         dbr_addr[0x40];
1854 
1855 	u8         hw_counter[0x20];
1856 
1857 	u8         sw_counter[0x20];
1858 
1859 	u8         reserved_at_100[0xc];
1860 	u8         log_wq_stride[0x4];
1861 	u8         reserved_at_110[0x3];
1862 	u8         log_wq_pg_sz[0x5];
1863 	u8         reserved_at_118[0x3];
1864 	u8         log_wq_sz[0x5];
1865 
1866 	u8         dbr_umem_valid[0x1];
1867 	u8         wq_umem_valid[0x1];
1868 	u8         reserved_at_122[0x1];
1869 	u8         log_hairpin_num_packets[0x5];
1870 	u8         reserved_at_128[0x3];
1871 	u8         log_hairpin_data_sz[0x5];
1872 
1873 	u8         reserved_at_130[0x4];
1874 	u8         log_wqe_num_of_strides[0x4];
1875 	u8         two_byte_shift_en[0x1];
1876 	u8         reserved_at_139[0x4];
1877 	u8         log_wqe_stride_size[0x3];
1878 
1879 	u8         reserved_at_140[0x4c0];
1880 
1881 	struct mlx5_ifc_cmd_pas_bits pas[];
1882 };
1883 
1884 struct mlx5_ifc_rq_num_bits {
1885 	u8         reserved_at_0[0x8];
1886 	u8         rq_num[0x18];
1887 };
1888 
1889 struct mlx5_ifc_mac_address_layout_bits {
1890 	u8         reserved_at_0[0x10];
1891 	u8         mac_addr_47_32[0x10];
1892 
1893 	u8         mac_addr_31_0[0x20];
1894 };
1895 
1896 struct mlx5_ifc_vlan_layout_bits {
1897 	u8         reserved_at_0[0x14];
1898 	u8         vlan[0x0c];
1899 
1900 	u8         reserved_at_20[0x20];
1901 };
1902 
1903 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1904 	u8         reserved_at_0[0xa0];
1905 
1906 	u8         min_time_between_cnps[0x20];
1907 
1908 	u8         reserved_at_c0[0x12];
1909 	u8         cnp_dscp[0x6];
1910 	u8         reserved_at_d8[0x4];
1911 	u8         cnp_prio_mode[0x1];
1912 	u8         cnp_802p_prio[0x3];
1913 
1914 	u8         reserved_at_e0[0x720];
1915 };
1916 
1917 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1918 	u8         reserved_at_0[0x60];
1919 
1920 	u8         reserved_at_60[0x4];
1921 	u8         clamp_tgt_rate[0x1];
1922 	u8         reserved_at_65[0x3];
1923 	u8         clamp_tgt_rate_after_time_inc[0x1];
1924 	u8         reserved_at_69[0x17];
1925 
1926 	u8         reserved_at_80[0x20];
1927 
1928 	u8         rpg_time_reset[0x20];
1929 
1930 	u8         rpg_byte_reset[0x20];
1931 
1932 	u8         rpg_threshold[0x20];
1933 
1934 	u8         rpg_max_rate[0x20];
1935 
1936 	u8         rpg_ai_rate[0x20];
1937 
1938 	u8         rpg_hai_rate[0x20];
1939 
1940 	u8         rpg_gd[0x20];
1941 
1942 	u8         rpg_min_dec_fac[0x20];
1943 
1944 	u8         rpg_min_rate[0x20];
1945 
1946 	u8         reserved_at_1c0[0xe0];
1947 
1948 	u8         rate_to_set_on_first_cnp[0x20];
1949 
1950 	u8         dce_tcp_g[0x20];
1951 
1952 	u8         dce_tcp_rtt[0x20];
1953 
1954 	u8         rate_reduce_monitor_period[0x20];
1955 
1956 	u8         reserved_at_320[0x20];
1957 
1958 	u8         initial_alpha_value[0x20];
1959 
1960 	u8         reserved_at_360[0x4a0];
1961 };
1962 
1963 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1964 	u8         reserved_at_0[0x80];
1965 
1966 	u8         rppp_max_rps[0x20];
1967 
1968 	u8         rpg_time_reset[0x20];
1969 
1970 	u8         rpg_byte_reset[0x20];
1971 
1972 	u8         rpg_threshold[0x20];
1973 
1974 	u8         rpg_max_rate[0x20];
1975 
1976 	u8         rpg_ai_rate[0x20];
1977 
1978 	u8         rpg_hai_rate[0x20];
1979 
1980 	u8         rpg_gd[0x20];
1981 
1982 	u8         rpg_min_dec_fac[0x20];
1983 
1984 	u8         rpg_min_rate[0x20];
1985 
1986 	u8         reserved_at_1c0[0x640];
1987 };
1988 
1989 enum {
1990 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1991 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1992 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1993 };
1994 
1995 struct mlx5_ifc_resize_field_select_bits {
1996 	u8         resize_field_select[0x20];
1997 };
1998 
1999 struct mlx5_ifc_resource_dump_bits {
2000 	u8         more_dump[0x1];
2001 	u8         inline_dump[0x1];
2002 	u8         reserved_at_2[0xa];
2003 	u8         seq_num[0x4];
2004 	u8         segment_type[0x10];
2005 
2006 	u8         reserved_at_20[0x10];
2007 	u8         vhca_id[0x10];
2008 
2009 	u8         index1[0x20];
2010 
2011 	u8         index2[0x20];
2012 
2013 	u8         num_of_obj1[0x10];
2014 	u8         num_of_obj2[0x10];
2015 
2016 	u8         reserved_at_a0[0x20];
2017 
2018 	u8         device_opaque[0x40];
2019 
2020 	u8         mkey[0x20];
2021 
2022 	u8         size[0x20];
2023 
2024 	u8         address[0x40];
2025 
2026 	u8         inline_data[52][0x20];
2027 };
2028 
2029 struct mlx5_ifc_resource_dump_menu_record_bits {
2030 	u8         reserved_at_0[0x4];
2031 	u8         num_of_obj2_supports_active[0x1];
2032 	u8         num_of_obj2_supports_all[0x1];
2033 	u8         must_have_num_of_obj2[0x1];
2034 	u8         support_num_of_obj2[0x1];
2035 	u8         num_of_obj1_supports_active[0x1];
2036 	u8         num_of_obj1_supports_all[0x1];
2037 	u8         must_have_num_of_obj1[0x1];
2038 	u8         support_num_of_obj1[0x1];
2039 	u8         must_have_index2[0x1];
2040 	u8         support_index2[0x1];
2041 	u8         must_have_index1[0x1];
2042 	u8         support_index1[0x1];
2043 	u8         segment_type[0x10];
2044 
2045 	u8         segment_name[4][0x20];
2046 
2047 	u8         index1_name[4][0x20];
2048 
2049 	u8         index2_name[4][0x20];
2050 };
2051 
2052 struct mlx5_ifc_resource_dump_segment_header_bits {
2053 	u8         length_dw[0x10];
2054 	u8         segment_type[0x10];
2055 };
2056 
2057 struct mlx5_ifc_resource_dump_command_segment_bits {
2058 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2059 
2060 	u8         segment_called[0x10];
2061 	u8         vhca_id[0x10];
2062 
2063 	u8         index1[0x20];
2064 
2065 	u8         index2[0x20];
2066 
2067 	u8         num_of_obj1[0x10];
2068 	u8         num_of_obj2[0x10];
2069 };
2070 
2071 struct mlx5_ifc_resource_dump_error_segment_bits {
2072 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2073 
2074 	u8         reserved_at_20[0x10];
2075 	u8         syndrome_id[0x10];
2076 
2077 	u8         reserved_at_40[0x40];
2078 
2079 	u8         error[8][0x20];
2080 };
2081 
2082 struct mlx5_ifc_resource_dump_info_segment_bits {
2083 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2084 
2085 	u8         reserved_at_20[0x18];
2086 	u8         dump_version[0x8];
2087 
2088 	u8         hw_version[0x20];
2089 
2090 	u8         fw_version[0x20];
2091 };
2092 
2093 struct mlx5_ifc_resource_dump_menu_segment_bits {
2094 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2095 
2096 	u8         reserved_at_20[0x10];
2097 	u8         num_of_records[0x10];
2098 
2099 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2100 };
2101 
2102 struct mlx5_ifc_resource_dump_resource_segment_bits {
2103 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2104 
2105 	u8         reserved_at_20[0x20];
2106 
2107 	u8         index1[0x20];
2108 
2109 	u8         index2[0x20];
2110 
2111 	u8         payload[][0x20];
2112 };
2113 
2114 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2115 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2116 };
2117 
2118 struct mlx5_ifc_menu_resource_dump_response_bits {
2119 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2120 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2121 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2122 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2123 };
2124 
2125 enum {
2126 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2127 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2128 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2129 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2130 };
2131 
2132 struct mlx5_ifc_modify_field_select_bits {
2133 	u8         modify_field_select[0x20];
2134 };
2135 
2136 struct mlx5_ifc_field_select_r_roce_np_bits {
2137 	u8         field_select_r_roce_np[0x20];
2138 };
2139 
2140 struct mlx5_ifc_field_select_r_roce_rp_bits {
2141 	u8         field_select_r_roce_rp[0x20];
2142 };
2143 
2144 enum {
2145 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2146 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2147 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2148 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2149 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2150 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2151 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2152 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2153 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2154 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2155 };
2156 
2157 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2158 	u8         field_select_8021qaurp[0x20];
2159 };
2160 
2161 struct mlx5_ifc_phys_layer_cntrs_bits {
2162 	u8         time_since_last_clear_high[0x20];
2163 
2164 	u8         time_since_last_clear_low[0x20];
2165 
2166 	u8         symbol_errors_high[0x20];
2167 
2168 	u8         symbol_errors_low[0x20];
2169 
2170 	u8         sync_headers_errors_high[0x20];
2171 
2172 	u8         sync_headers_errors_low[0x20];
2173 
2174 	u8         edpl_bip_errors_lane0_high[0x20];
2175 
2176 	u8         edpl_bip_errors_lane0_low[0x20];
2177 
2178 	u8         edpl_bip_errors_lane1_high[0x20];
2179 
2180 	u8         edpl_bip_errors_lane1_low[0x20];
2181 
2182 	u8         edpl_bip_errors_lane2_high[0x20];
2183 
2184 	u8         edpl_bip_errors_lane2_low[0x20];
2185 
2186 	u8         edpl_bip_errors_lane3_high[0x20];
2187 
2188 	u8         edpl_bip_errors_lane3_low[0x20];
2189 
2190 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2191 
2192 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2193 
2194 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2195 
2196 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2197 
2198 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2199 
2200 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2201 
2202 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2203 
2204 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2205 
2206 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2207 
2208 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2209 
2210 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2211 
2212 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2213 
2214 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2215 
2216 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2217 
2218 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2219 
2220 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2221 
2222 	u8         rs_fec_corrected_blocks_high[0x20];
2223 
2224 	u8         rs_fec_corrected_blocks_low[0x20];
2225 
2226 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2227 
2228 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2229 
2230 	u8         rs_fec_no_errors_blocks_high[0x20];
2231 
2232 	u8         rs_fec_no_errors_blocks_low[0x20];
2233 
2234 	u8         rs_fec_single_error_blocks_high[0x20];
2235 
2236 	u8         rs_fec_single_error_blocks_low[0x20];
2237 
2238 	u8         rs_fec_corrected_symbols_total_high[0x20];
2239 
2240 	u8         rs_fec_corrected_symbols_total_low[0x20];
2241 
2242 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2243 
2244 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2245 
2246 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2247 
2248 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2249 
2250 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2251 
2252 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2253 
2254 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2255 
2256 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2257 
2258 	u8         link_down_events[0x20];
2259 
2260 	u8         successful_recovery_events[0x20];
2261 
2262 	u8         reserved_at_640[0x180];
2263 };
2264 
2265 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2266 	u8         time_since_last_clear_high[0x20];
2267 
2268 	u8         time_since_last_clear_low[0x20];
2269 
2270 	u8         phy_received_bits_high[0x20];
2271 
2272 	u8         phy_received_bits_low[0x20];
2273 
2274 	u8         phy_symbol_errors_high[0x20];
2275 
2276 	u8         phy_symbol_errors_low[0x20];
2277 
2278 	u8         phy_corrected_bits_high[0x20];
2279 
2280 	u8         phy_corrected_bits_low[0x20];
2281 
2282 	u8         phy_corrected_bits_lane0_high[0x20];
2283 
2284 	u8         phy_corrected_bits_lane0_low[0x20];
2285 
2286 	u8         phy_corrected_bits_lane1_high[0x20];
2287 
2288 	u8         phy_corrected_bits_lane1_low[0x20];
2289 
2290 	u8         phy_corrected_bits_lane2_high[0x20];
2291 
2292 	u8         phy_corrected_bits_lane2_low[0x20];
2293 
2294 	u8         phy_corrected_bits_lane3_high[0x20];
2295 
2296 	u8         phy_corrected_bits_lane3_low[0x20];
2297 
2298 	u8         reserved_at_200[0x5c0];
2299 };
2300 
2301 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2302 	u8	   symbol_error_counter[0x10];
2303 
2304 	u8         link_error_recovery_counter[0x8];
2305 
2306 	u8         link_downed_counter[0x8];
2307 
2308 	u8         port_rcv_errors[0x10];
2309 
2310 	u8         port_rcv_remote_physical_errors[0x10];
2311 
2312 	u8         port_rcv_switch_relay_errors[0x10];
2313 
2314 	u8         port_xmit_discards[0x10];
2315 
2316 	u8         port_xmit_constraint_errors[0x8];
2317 
2318 	u8         port_rcv_constraint_errors[0x8];
2319 
2320 	u8         reserved_at_70[0x8];
2321 
2322 	u8         link_overrun_errors[0x8];
2323 
2324 	u8	   reserved_at_80[0x10];
2325 
2326 	u8         vl_15_dropped[0x10];
2327 
2328 	u8	   reserved_at_a0[0x80];
2329 
2330 	u8         port_xmit_wait[0x20];
2331 };
2332 
2333 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2334 	u8         transmit_queue_high[0x20];
2335 
2336 	u8         transmit_queue_low[0x20];
2337 
2338 	u8         no_buffer_discard_uc_high[0x20];
2339 
2340 	u8         no_buffer_discard_uc_low[0x20];
2341 
2342 	u8         reserved_at_80[0x740];
2343 };
2344 
2345 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2346 	u8         wred_discard_high[0x20];
2347 
2348 	u8         wred_discard_low[0x20];
2349 
2350 	u8         ecn_marked_tc_high[0x20];
2351 
2352 	u8         ecn_marked_tc_low[0x20];
2353 
2354 	u8         reserved_at_80[0x740];
2355 };
2356 
2357 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2358 	u8         rx_octets_high[0x20];
2359 
2360 	u8         rx_octets_low[0x20];
2361 
2362 	u8         reserved_at_40[0xc0];
2363 
2364 	u8         rx_frames_high[0x20];
2365 
2366 	u8         rx_frames_low[0x20];
2367 
2368 	u8         tx_octets_high[0x20];
2369 
2370 	u8         tx_octets_low[0x20];
2371 
2372 	u8         reserved_at_180[0xc0];
2373 
2374 	u8         tx_frames_high[0x20];
2375 
2376 	u8         tx_frames_low[0x20];
2377 
2378 	u8         rx_pause_high[0x20];
2379 
2380 	u8         rx_pause_low[0x20];
2381 
2382 	u8         rx_pause_duration_high[0x20];
2383 
2384 	u8         rx_pause_duration_low[0x20];
2385 
2386 	u8         tx_pause_high[0x20];
2387 
2388 	u8         tx_pause_low[0x20];
2389 
2390 	u8         tx_pause_duration_high[0x20];
2391 
2392 	u8         tx_pause_duration_low[0x20];
2393 
2394 	u8         rx_pause_transition_high[0x20];
2395 
2396 	u8         rx_pause_transition_low[0x20];
2397 
2398 	u8         rx_discards_high[0x20];
2399 
2400 	u8         rx_discards_low[0x20];
2401 
2402 	u8         device_stall_minor_watermark_cnt_high[0x20];
2403 
2404 	u8         device_stall_minor_watermark_cnt_low[0x20];
2405 
2406 	u8         device_stall_critical_watermark_cnt_high[0x20];
2407 
2408 	u8         device_stall_critical_watermark_cnt_low[0x20];
2409 
2410 	u8         reserved_at_480[0x340];
2411 };
2412 
2413 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2414 	u8         port_transmit_wait_high[0x20];
2415 
2416 	u8         port_transmit_wait_low[0x20];
2417 
2418 	u8         reserved_at_40[0x100];
2419 
2420 	u8         rx_buffer_almost_full_high[0x20];
2421 
2422 	u8         rx_buffer_almost_full_low[0x20];
2423 
2424 	u8         rx_buffer_full_high[0x20];
2425 
2426 	u8         rx_buffer_full_low[0x20];
2427 
2428 	u8         rx_icrc_encapsulated_high[0x20];
2429 
2430 	u8         rx_icrc_encapsulated_low[0x20];
2431 
2432 	u8         reserved_at_200[0x5c0];
2433 };
2434 
2435 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2436 	u8         dot3stats_alignment_errors_high[0x20];
2437 
2438 	u8         dot3stats_alignment_errors_low[0x20];
2439 
2440 	u8         dot3stats_fcs_errors_high[0x20];
2441 
2442 	u8         dot3stats_fcs_errors_low[0x20];
2443 
2444 	u8         dot3stats_single_collision_frames_high[0x20];
2445 
2446 	u8         dot3stats_single_collision_frames_low[0x20];
2447 
2448 	u8         dot3stats_multiple_collision_frames_high[0x20];
2449 
2450 	u8         dot3stats_multiple_collision_frames_low[0x20];
2451 
2452 	u8         dot3stats_sqe_test_errors_high[0x20];
2453 
2454 	u8         dot3stats_sqe_test_errors_low[0x20];
2455 
2456 	u8         dot3stats_deferred_transmissions_high[0x20];
2457 
2458 	u8         dot3stats_deferred_transmissions_low[0x20];
2459 
2460 	u8         dot3stats_late_collisions_high[0x20];
2461 
2462 	u8         dot3stats_late_collisions_low[0x20];
2463 
2464 	u8         dot3stats_excessive_collisions_high[0x20];
2465 
2466 	u8         dot3stats_excessive_collisions_low[0x20];
2467 
2468 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2469 
2470 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2471 
2472 	u8         dot3stats_carrier_sense_errors_high[0x20];
2473 
2474 	u8         dot3stats_carrier_sense_errors_low[0x20];
2475 
2476 	u8         dot3stats_frame_too_longs_high[0x20];
2477 
2478 	u8         dot3stats_frame_too_longs_low[0x20];
2479 
2480 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
2481 
2482 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
2483 
2484 	u8         dot3stats_symbol_errors_high[0x20];
2485 
2486 	u8         dot3stats_symbol_errors_low[0x20];
2487 
2488 	u8         dot3control_in_unknown_opcodes_high[0x20];
2489 
2490 	u8         dot3control_in_unknown_opcodes_low[0x20];
2491 
2492 	u8         dot3in_pause_frames_high[0x20];
2493 
2494 	u8         dot3in_pause_frames_low[0x20];
2495 
2496 	u8         dot3out_pause_frames_high[0x20];
2497 
2498 	u8         dot3out_pause_frames_low[0x20];
2499 
2500 	u8         reserved_at_400[0x3c0];
2501 };
2502 
2503 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2504 	u8         ether_stats_drop_events_high[0x20];
2505 
2506 	u8         ether_stats_drop_events_low[0x20];
2507 
2508 	u8         ether_stats_octets_high[0x20];
2509 
2510 	u8         ether_stats_octets_low[0x20];
2511 
2512 	u8         ether_stats_pkts_high[0x20];
2513 
2514 	u8         ether_stats_pkts_low[0x20];
2515 
2516 	u8         ether_stats_broadcast_pkts_high[0x20];
2517 
2518 	u8         ether_stats_broadcast_pkts_low[0x20];
2519 
2520 	u8         ether_stats_multicast_pkts_high[0x20];
2521 
2522 	u8         ether_stats_multicast_pkts_low[0x20];
2523 
2524 	u8         ether_stats_crc_align_errors_high[0x20];
2525 
2526 	u8         ether_stats_crc_align_errors_low[0x20];
2527 
2528 	u8         ether_stats_undersize_pkts_high[0x20];
2529 
2530 	u8         ether_stats_undersize_pkts_low[0x20];
2531 
2532 	u8         ether_stats_oversize_pkts_high[0x20];
2533 
2534 	u8         ether_stats_oversize_pkts_low[0x20];
2535 
2536 	u8         ether_stats_fragments_high[0x20];
2537 
2538 	u8         ether_stats_fragments_low[0x20];
2539 
2540 	u8         ether_stats_jabbers_high[0x20];
2541 
2542 	u8         ether_stats_jabbers_low[0x20];
2543 
2544 	u8         ether_stats_collisions_high[0x20];
2545 
2546 	u8         ether_stats_collisions_low[0x20];
2547 
2548 	u8         ether_stats_pkts64octets_high[0x20];
2549 
2550 	u8         ether_stats_pkts64octets_low[0x20];
2551 
2552 	u8         ether_stats_pkts65to127octets_high[0x20];
2553 
2554 	u8         ether_stats_pkts65to127octets_low[0x20];
2555 
2556 	u8         ether_stats_pkts128to255octets_high[0x20];
2557 
2558 	u8         ether_stats_pkts128to255octets_low[0x20];
2559 
2560 	u8         ether_stats_pkts256to511octets_high[0x20];
2561 
2562 	u8         ether_stats_pkts256to511octets_low[0x20];
2563 
2564 	u8         ether_stats_pkts512to1023octets_high[0x20];
2565 
2566 	u8         ether_stats_pkts512to1023octets_low[0x20];
2567 
2568 	u8         ether_stats_pkts1024to1518octets_high[0x20];
2569 
2570 	u8         ether_stats_pkts1024to1518octets_low[0x20];
2571 
2572 	u8         ether_stats_pkts1519to2047octets_high[0x20];
2573 
2574 	u8         ether_stats_pkts1519to2047octets_low[0x20];
2575 
2576 	u8         ether_stats_pkts2048to4095octets_high[0x20];
2577 
2578 	u8         ether_stats_pkts2048to4095octets_low[0x20];
2579 
2580 	u8         ether_stats_pkts4096to8191octets_high[0x20];
2581 
2582 	u8         ether_stats_pkts4096to8191octets_low[0x20];
2583 
2584 	u8         ether_stats_pkts8192to10239octets_high[0x20];
2585 
2586 	u8         ether_stats_pkts8192to10239octets_low[0x20];
2587 
2588 	u8         reserved_at_540[0x280];
2589 };
2590 
2591 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2592 	u8         if_in_octets_high[0x20];
2593 
2594 	u8         if_in_octets_low[0x20];
2595 
2596 	u8         if_in_ucast_pkts_high[0x20];
2597 
2598 	u8         if_in_ucast_pkts_low[0x20];
2599 
2600 	u8         if_in_discards_high[0x20];
2601 
2602 	u8         if_in_discards_low[0x20];
2603 
2604 	u8         if_in_errors_high[0x20];
2605 
2606 	u8         if_in_errors_low[0x20];
2607 
2608 	u8         if_in_unknown_protos_high[0x20];
2609 
2610 	u8         if_in_unknown_protos_low[0x20];
2611 
2612 	u8         if_out_octets_high[0x20];
2613 
2614 	u8         if_out_octets_low[0x20];
2615 
2616 	u8         if_out_ucast_pkts_high[0x20];
2617 
2618 	u8         if_out_ucast_pkts_low[0x20];
2619 
2620 	u8         if_out_discards_high[0x20];
2621 
2622 	u8         if_out_discards_low[0x20];
2623 
2624 	u8         if_out_errors_high[0x20];
2625 
2626 	u8         if_out_errors_low[0x20];
2627 
2628 	u8         if_in_multicast_pkts_high[0x20];
2629 
2630 	u8         if_in_multicast_pkts_low[0x20];
2631 
2632 	u8         if_in_broadcast_pkts_high[0x20];
2633 
2634 	u8         if_in_broadcast_pkts_low[0x20];
2635 
2636 	u8         if_out_multicast_pkts_high[0x20];
2637 
2638 	u8         if_out_multicast_pkts_low[0x20];
2639 
2640 	u8         if_out_broadcast_pkts_high[0x20];
2641 
2642 	u8         if_out_broadcast_pkts_low[0x20];
2643 
2644 	u8         reserved_at_340[0x480];
2645 };
2646 
2647 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2648 	u8         a_frames_transmitted_ok_high[0x20];
2649 
2650 	u8         a_frames_transmitted_ok_low[0x20];
2651 
2652 	u8         a_frames_received_ok_high[0x20];
2653 
2654 	u8         a_frames_received_ok_low[0x20];
2655 
2656 	u8         a_frame_check_sequence_errors_high[0x20];
2657 
2658 	u8         a_frame_check_sequence_errors_low[0x20];
2659 
2660 	u8         a_alignment_errors_high[0x20];
2661 
2662 	u8         a_alignment_errors_low[0x20];
2663 
2664 	u8         a_octets_transmitted_ok_high[0x20];
2665 
2666 	u8         a_octets_transmitted_ok_low[0x20];
2667 
2668 	u8         a_octets_received_ok_high[0x20];
2669 
2670 	u8         a_octets_received_ok_low[0x20];
2671 
2672 	u8         a_multicast_frames_xmitted_ok_high[0x20];
2673 
2674 	u8         a_multicast_frames_xmitted_ok_low[0x20];
2675 
2676 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
2677 
2678 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
2679 
2680 	u8         a_multicast_frames_received_ok_high[0x20];
2681 
2682 	u8         a_multicast_frames_received_ok_low[0x20];
2683 
2684 	u8         a_broadcast_frames_received_ok_high[0x20];
2685 
2686 	u8         a_broadcast_frames_received_ok_low[0x20];
2687 
2688 	u8         a_in_range_length_errors_high[0x20];
2689 
2690 	u8         a_in_range_length_errors_low[0x20];
2691 
2692 	u8         a_out_of_range_length_field_high[0x20];
2693 
2694 	u8         a_out_of_range_length_field_low[0x20];
2695 
2696 	u8         a_frame_too_long_errors_high[0x20];
2697 
2698 	u8         a_frame_too_long_errors_low[0x20];
2699 
2700 	u8         a_symbol_error_during_carrier_high[0x20];
2701 
2702 	u8         a_symbol_error_during_carrier_low[0x20];
2703 
2704 	u8         a_mac_control_frames_transmitted_high[0x20];
2705 
2706 	u8         a_mac_control_frames_transmitted_low[0x20];
2707 
2708 	u8         a_mac_control_frames_received_high[0x20];
2709 
2710 	u8         a_mac_control_frames_received_low[0x20];
2711 
2712 	u8         a_unsupported_opcodes_received_high[0x20];
2713 
2714 	u8         a_unsupported_opcodes_received_low[0x20];
2715 
2716 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
2717 
2718 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
2719 
2720 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2721 
2722 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2723 
2724 	u8         reserved_at_4c0[0x300];
2725 };
2726 
2727 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2728 	u8         life_time_counter_high[0x20];
2729 
2730 	u8         life_time_counter_low[0x20];
2731 
2732 	u8         rx_errors[0x20];
2733 
2734 	u8         tx_errors[0x20];
2735 
2736 	u8         l0_to_recovery_eieos[0x20];
2737 
2738 	u8         l0_to_recovery_ts[0x20];
2739 
2740 	u8         l0_to_recovery_framing[0x20];
2741 
2742 	u8         l0_to_recovery_retrain[0x20];
2743 
2744 	u8         crc_error_dllp[0x20];
2745 
2746 	u8         crc_error_tlp[0x20];
2747 
2748 	u8         tx_overflow_buffer_pkt_high[0x20];
2749 
2750 	u8         tx_overflow_buffer_pkt_low[0x20];
2751 
2752 	u8         outbound_stalled_reads[0x20];
2753 
2754 	u8         outbound_stalled_writes[0x20];
2755 
2756 	u8         outbound_stalled_reads_events[0x20];
2757 
2758 	u8         outbound_stalled_writes_events[0x20];
2759 
2760 	u8         reserved_at_200[0x5c0];
2761 };
2762 
2763 struct mlx5_ifc_cmd_inter_comp_event_bits {
2764 	u8         command_completion_vector[0x20];
2765 
2766 	u8         reserved_at_20[0xc0];
2767 };
2768 
2769 struct mlx5_ifc_stall_vl_event_bits {
2770 	u8         reserved_at_0[0x18];
2771 	u8         port_num[0x1];
2772 	u8         reserved_at_19[0x3];
2773 	u8         vl[0x4];
2774 
2775 	u8         reserved_at_20[0xa0];
2776 };
2777 
2778 struct mlx5_ifc_db_bf_congestion_event_bits {
2779 	u8         event_subtype[0x8];
2780 	u8         reserved_at_8[0x8];
2781 	u8         congestion_level[0x8];
2782 	u8         reserved_at_18[0x8];
2783 
2784 	u8         reserved_at_20[0xa0];
2785 };
2786 
2787 struct mlx5_ifc_gpio_event_bits {
2788 	u8         reserved_at_0[0x60];
2789 
2790 	u8         gpio_event_hi[0x20];
2791 
2792 	u8         gpio_event_lo[0x20];
2793 
2794 	u8         reserved_at_a0[0x40];
2795 };
2796 
2797 struct mlx5_ifc_port_state_change_event_bits {
2798 	u8         reserved_at_0[0x40];
2799 
2800 	u8         port_num[0x4];
2801 	u8         reserved_at_44[0x1c];
2802 
2803 	u8         reserved_at_60[0x80];
2804 };
2805 
2806 struct mlx5_ifc_dropped_packet_logged_bits {
2807 	u8         reserved_at_0[0xe0];
2808 };
2809 
2810 enum {
2811 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2812 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2813 };
2814 
2815 struct mlx5_ifc_cq_error_bits {
2816 	u8         reserved_at_0[0x8];
2817 	u8         cqn[0x18];
2818 
2819 	u8         reserved_at_20[0x20];
2820 
2821 	u8         reserved_at_40[0x18];
2822 	u8         syndrome[0x8];
2823 
2824 	u8         reserved_at_60[0x80];
2825 };
2826 
2827 struct mlx5_ifc_rdma_page_fault_event_bits {
2828 	u8         bytes_committed[0x20];
2829 
2830 	u8         r_key[0x20];
2831 
2832 	u8         reserved_at_40[0x10];
2833 	u8         packet_len[0x10];
2834 
2835 	u8         rdma_op_len[0x20];
2836 
2837 	u8         rdma_va[0x40];
2838 
2839 	u8         reserved_at_c0[0x5];
2840 	u8         rdma[0x1];
2841 	u8         write[0x1];
2842 	u8         requestor[0x1];
2843 	u8         qp_number[0x18];
2844 };
2845 
2846 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2847 	u8         bytes_committed[0x20];
2848 
2849 	u8         reserved_at_20[0x10];
2850 	u8         wqe_index[0x10];
2851 
2852 	u8         reserved_at_40[0x10];
2853 	u8         len[0x10];
2854 
2855 	u8         reserved_at_60[0x60];
2856 
2857 	u8         reserved_at_c0[0x5];
2858 	u8         rdma[0x1];
2859 	u8         write_read[0x1];
2860 	u8         requestor[0x1];
2861 	u8         qpn[0x18];
2862 };
2863 
2864 struct mlx5_ifc_qp_events_bits {
2865 	u8         reserved_at_0[0xa0];
2866 
2867 	u8         type[0x8];
2868 	u8         reserved_at_a8[0x18];
2869 
2870 	u8         reserved_at_c0[0x8];
2871 	u8         qpn_rqn_sqn[0x18];
2872 };
2873 
2874 struct mlx5_ifc_dct_events_bits {
2875 	u8         reserved_at_0[0xc0];
2876 
2877 	u8         reserved_at_c0[0x8];
2878 	u8         dct_number[0x18];
2879 };
2880 
2881 struct mlx5_ifc_comp_event_bits {
2882 	u8         reserved_at_0[0xc0];
2883 
2884 	u8         reserved_at_c0[0x8];
2885 	u8         cq_number[0x18];
2886 };
2887 
2888 enum {
2889 	MLX5_QPC_STATE_RST        = 0x0,
2890 	MLX5_QPC_STATE_INIT       = 0x1,
2891 	MLX5_QPC_STATE_RTR        = 0x2,
2892 	MLX5_QPC_STATE_RTS        = 0x3,
2893 	MLX5_QPC_STATE_SQER       = 0x4,
2894 	MLX5_QPC_STATE_ERR        = 0x6,
2895 	MLX5_QPC_STATE_SQD        = 0x7,
2896 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
2897 };
2898 
2899 enum {
2900 	MLX5_QPC_ST_RC            = 0x0,
2901 	MLX5_QPC_ST_UC            = 0x1,
2902 	MLX5_QPC_ST_UD            = 0x2,
2903 	MLX5_QPC_ST_XRC           = 0x3,
2904 	MLX5_QPC_ST_DCI           = 0x5,
2905 	MLX5_QPC_ST_QP0           = 0x7,
2906 	MLX5_QPC_ST_QP1           = 0x8,
2907 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2908 	MLX5_QPC_ST_REG_UMR       = 0xc,
2909 };
2910 
2911 enum {
2912 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
2913 	MLX5_QPC_PM_STATE_REARM     = 0x1,
2914 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2915 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2916 };
2917 
2918 enum {
2919 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2920 };
2921 
2922 enum {
2923 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2924 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2925 };
2926 
2927 enum {
2928 	MLX5_QPC_MTU_256_BYTES        = 0x1,
2929 	MLX5_QPC_MTU_512_BYTES        = 0x2,
2930 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
2931 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
2932 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
2933 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2934 };
2935 
2936 enum {
2937 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2938 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2939 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2940 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2941 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2942 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2943 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2944 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2945 };
2946 
2947 enum {
2948 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2949 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2950 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2951 };
2952 
2953 enum {
2954 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
2955 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2956 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2957 };
2958 
2959 enum {
2960 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2961 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
2962 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
2963 };
2964 
2965 struct mlx5_ifc_qpc_bits {
2966 	u8         state[0x4];
2967 	u8         lag_tx_port_affinity[0x4];
2968 	u8         st[0x8];
2969 	u8         reserved_at_10[0x2];
2970 	u8	   isolate_vl_tc[0x1];
2971 	u8         pm_state[0x2];
2972 	u8         reserved_at_15[0x1];
2973 	u8         req_e2e_credit_mode[0x2];
2974 	u8         offload_type[0x4];
2975 	u8         end_padding_mode[0x2];
2976 	u8         reserved_at_1e[0x2];
2977 
2978 	u8         wq_signature[0x1];
2979 	u8         block_lb_mc[0x1];
2980 	u8         atomic_like_write_en[0x1];
2981 	u8         latency_sensitive[0x1];
2982 	u8         reserved_at_24[0x1];
2983 	u8         drain_sigerr[0x1];
2984 	u8         reserved_at_26[0x2];
2985 	u8         pd[0x18];
2986 
2987 	u8         mtu[0x3];
2988 	u8         log_msg_max[0x5];
2989 	u8         reserved_at_48[0x1];
2990 	u8         log_rq_size[0x4];
2991 	u8         log_rq_stride[0x3];
2992 	u8         no_sq[0x1];
2993 	u8         log_sq_size[0x4];
2994 	u8         reserved_at_55[0x3];
2995 	u8	   ts_format[0x2];
2996 	u8         reserved_at_5a[0x1];
2997 	u8         rlky[0x1];
2998 	u8         ulp_stateless_offload_mode[0x4];
2999 
3000 	u8         counter_set_id[0x8];
3001 	u8         uar_page[0x18];
3002 
3003 	u8         reserved_at_80[0x8];
3004 	u8         user_index[0x18];
3005 
3006 	u8         reserved_at_a0[0x3];
3007 	u8         log_page_size[0x5];
3008 	u8         remote_qpn[0x18];
3009 
3010 	struct mlx5_ifc_ads_bits primary_address_path;
3011 
3012 	struct mlx5_ifc_ads_bits secondary_address_path;
3013 
3014 	u8         log_ack_req_freq[0x4];
3015 	u8         reserved_at_384[0x4];
3016 	u8         log_sra_max[0x3];
3017 	u8         reserved_at_38b[0x2];
3018 	u8         retry_count[0x3];
3019 	u8         rnr_retry[0x3];
3020 	u8         reserved_at_393[0x1];
3021 	u8         fre[0x1];
3022 	u8         cur_rnr_retry[0x3];
3023 	u8         cur_retry_count[0x3];
3024 	u8         reserved_at_39b[0x5];
3025 
3026 	u8         reserved_at_3a0[0x20];
3027 
3028 	u8         reserved_at_3c0[0x8];
3029 	u8         next_send_psn[0x18];
3030 
3031 	u8         reserved_at_3e0[0x3];
3032 	u8	   log_num_dci_stream_channels[0x5];
3033 	u8         cqn_snd[0x18];
3034 
3035 	u8         reserved_at_400[0x3];
3036 	u8	   log_num_dci_errored_streams[0x5];
3037 	u8         deth_sqpn[0x18];
3038 
3039 	u8         reserved_at_420[0x20];
3040 
3041 	u8         reserved_at_440[0x8];
3042 	u8         last_acked_psn[0x18];
3043 
3044 	u8         reserved_at_460[0x8];
3045 	u8         ssn[0x18];
3046 
3047 	u8         reserved_at_480[0x8];
3048 	u8         log_rra_max[0x3];
3049 	u8         reserved_at_48b[0x1];
3050 	u8         atomic_mode[0x4];
3051 	u8         rre[0x1];
3052 	u8         rwe[0x1];
3053 	u8         rae[0x1];
3054 	u8         reserved_at_493[0x1];
3055 	u8         page_offset[0x6];
3056 	u8         reserved_at_49a[0x3];
3057 	u8         cd_slave_receive[0x1];
3058 	u8         cd_slave_send[0x1];
3059 	u8         cd_master[0x1];
3060 
3061 	u8         reserved_at_4a0[0x3];
3062 	u8         min_rnr_nak[0x5];
3063 	u8         next_rcv_psn[0x18];
3064 
3065 	u8         reserved_at_4c0[0x8];
3066 	u8         xrcd[0x18];
3067 
3068 	u8         reserved_at_4e0[0x8];
3069 	u8         cqn_rcv[0x18];
3070 
3071 	u8         dbr_addr[0x40];
3072 
3073 	u8         q_key[0x20];
3074 
3075 	u8         reserved_at_560[0x5];
3076 	u8         rq_type[0x3];
3077 	u8         srqn_rmpn_xrqn[0x18];
3078 
3079 	u8         reserved_at_580[0x8];
3080 	u8         rmsn[0x18];
3081 
3082 	u8         hw_sq_wqebb_counter[0x10];
3083 	u8         sw_sq_wqebb_counter[0x10];
3084 
3085 	u8         hw_rq_counter[0x20];
3086 
3087 	u8         sw_rq_counter[0x20];
3088 
3089 	u8         reserved_at_600[0x20];
3090 
3091 	u8         reserved_at_620[0xf];
3092 	u8         cgs[0x1];
3093 	u8         cs_req[0x8];
3094 	u8         cs_res[0x8];
3095 
3096 	u8         dc_access_key[0x40];
3097 
3098 	u8         reserved_at_680[0x3];
3099 	u8         dbr_umem_valid[0x1];
3100 
3101 	u8         reserved_at_684[0xbc];
3102 };
3103 
3104 struct mlx5_ifc_roce_addr_layout_bits {
3105 	u8         source_l3_address[16][0x8];
3106 
3107 	u8         reserved_at_80[0x3];
3108 	u8         vlan_valid[0x1];
3109 	u8         vlan_id[0xc];
3110 	u8         source_mac_47_32[0x10];
3111 
3112 	u8         source_mac_31_0[0x20];
3113 
3114 	u8         reserved_at_c0[0x14];
3115 	u8         roce_l3_type[0x4];
3116 	u8         roce_version[0x8];
3117 
3118 	u8         reserved_at_e0[0x20];
3119 };
3120 
3121 union mlx5_ifc_hca_cap_union_bits {
3122 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3123 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3124 	struct mlx5_ifc_odp_cap_bits odp_cap;
3125 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3126 	struct mlx5_ifc_roce_cap_bits roce_cap;
3127 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3128 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3129 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3130 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3131 	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3132 	struct mlx5_ifc_qos_cap_bits qos_cap;
3133 	struct mlx5_ifc_debug_cap_bits debug_cap;
3134 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3135 	struct mlx5_ifc_tls_cap_bits tls_cap;
3136 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3137 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3138 	u8         reserved_at_0[0x8000];
3139 };
3140 
3141 enum {
3142 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3143 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3144 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3145 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3146 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3147 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3148 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3149 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3150 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3151 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3152 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3153 	MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3154 	MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3155 };
3156 
3157 enum {
3158 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3159 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3160 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3161 };
3162 
3163 struct mlx5_ifc_vlan_bits {
3164 	u8         ethtype[0x10];
3165 	u8         prio[0x3];
3166 	u8         cfi[0x1];
3167 	u8         vid[0xc];
3168 };
3169 
3170 struct mlx5_ifc_flow_context_bits {
3171 	struct mlx5_ifc_vlan_bits push_vlan;
3172 
3173 	u8         group_id[0x20];
3174 
3175 	u8         reserved_at_40[0x8];
3176 	u8         flow_tag[0x18];
3177 
3178 	u8         reserved_at_60[0x10];
3179 	u8         action[0x10];
3180 
3181 	u8         extended_destination[0x1];
3182 	u8         reserved_at_81[0x1];
3183 	u8         flow_source[0x2];
3184 	u8         reserved_at_84[0x4];
3185 	u8         destination_list_size[0x18];
3186 
3187 	u8         reserved_at_a0[0x8];
3188 	u8         flow_counter_list_size[0x18];
3189 
3190 	u8         packet_reformat_id[0x20];
3191 
3192 	u8         modify_header_id[0x20];
3193 
3194 	struct mlx5_ifc_vlan_bits push_vlan_2;
3195 
3196 	u8         ipsec_obj_id[0x20];
3197 	u8         reserved_at_140[0xc0];
3198 
3199 	struct mlx5_ifc_fte_match_param_bits match_value;
3200 
3201 	u8         reserved_at_1200[0x600];
3202 
3203 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3204 };
3205 
3206 enum {
3207 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3208 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3209 };
3210 
3211 struct mlx5_ifc_xrc_srqc_bits {
3212 	u8         state[0x4];
3213 	u8         log_xrc_srq_size[0x4];
3214 	u8         reserved_at_8[0x18];
3215 
3216 	u8         wq_signature[0x1];
3217 	u8         cont_srq[0x1];
3218 	u8         reserved_at_22[0x1];
3219 	u8         rlky[0x1];
3220 	u8         basic_cyclic_rcv_wqe[0x1];
3221 	u8         log_rq_stride[0x3];
3222 	u8         xrcd[0x18];
3223 
3224 	u8         page_offset[0x6];
3225 	u8         reserved_at_46[0x1];
3226 	u8         dbr_umem_valid[0x1];
3227 	u8         cqn[0x18];
3228 
3229 	u8         reserved_at_60[0x20];
3230 
3231 	u8         user_index_equal_xrc_srqn[0x1];
3232 	u8         reserved_at_81[0x1];
3233 	u8         log_page_size[0x6];
3234 	u8         user_index[0x18];
3235 
3236 	u8         reserved_at_a0[0x20];
3237 
3238 	u8         reserved_at_c0[0x8];
3239 	u8         pd[0x18];
3240 
3241 	u8         lwm[0x10];
3242 	u8         wqe_cnt[0x10];
3243 
3244 	u8         reserved_at_100[0x40];
3245 
3246 	u8         db_record_addr_h[0x20];
3247 
3248 	u8         db_record_addr_l[0x1e];
3249 	u8         reserved_at_17e[0x2];
3250 
3251 	u8         reserved_at_180[0x80];
3252 };
3253 
3254 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3255 	u8         counter_error_queues[0x20];
3256 
3257 	u8         total_error_queues[0x20];
3258 
3259 	u8         send_queue_priority_update_flow[0x20];
3260 
3261 	u8         reserved_at_60[0x20];
3262 
3263 	u8         nic_receive_steering_discard[0x40];
3264 
3265 	u8         receive_discard_vport_down[0x40];
3266 
3267 	u8         transmit_discard_vport_down[0x40];
3268 
3269 	u8         reserved_at_140[0xa0];
3270 
3271 	u8         internal_rq_out_of_buffer[0x20];
3272 
3273 	u8         reserved_at_200[0xe00];
3274 };
3275 
3276 struct mlx5_ifc_traffic_counter_bits {
3277 	u8         packets[0x40];
3278 
3279 	u8         octets[0x40];
3280 };
3281 
3282 struct mlx5_ifc_tisc_bits {
3283 	u8         strict_lag_tx_port_affinity[0x1];
3284 	u8         tls_en[0x1];
3285 	u8         reserved_at_2[0x2];
3286 	u8         lag_tx_port_affinity[0x04];
3287 
3288 	u8         reserved_at_8[0x4];
3289 	u8         prio[0x4];
3290 	u8         reserved_at_10[0x10];
3291 
3292 	u8         reserved_at_20[0x100];
3293 
3294 	u8         reserved_at_120[0x8];
3295 	u8         transport_domain[0x18];
3296 
3297 	u8         reserved_at_140[0x8];
3298 	u8         underlay_qpn[0x18];
3299 
3300 	u8         reserved_at_160[0x8];
3301 	u8         pd[0x18];
3302 
3303 	u8         reserved_at_180[0x380];
3304 };
3305 
3306 enum {
3307 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3308 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3309 };
3310 
3311 enum {
3312 	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3313 	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3314 };
3315 
3316 enum {
3317 	MLX5_RX_HASH_FN_NONE           = 0x0,
3318 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3319 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3320 };
3321 
3322 enum {
3323 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3324 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3325 };
3326 
3327 struct mlx5_ifc_tirc_bits {
3328 	u8         reserved_at_0[0x20];
3329 
3330 	u8         disp_type[0x4];
3331 	u8         tls_en[0x1];
3332 	u8         reserved_at_25[0x1b];
3333 
3334 	u8         reserved_at_40[0x40];
3335 
3336 	u8         reserved_at_80[0x4];
3337 	u8         lro_timeout_period_usecs[0x10];
3338 	u8         lro_enable_mask[0x4];
3339 	u8         lro_max_ip_payload_size[0x8];
3340 
3341 	u8         reserved_at_a0[0x40];
3342 
3343 	u8         reserved_at_e0[0x8];
3344 	u8         inline_rqn[0x18];
3345 
3346 	u8         rx_hash_symmetric[0x1];
3347 	u8         reserved_at_101[0x1];
3348 	u8         tunneled_offload_en[0x1];
3349 	u8         reserved_at_103[0x5];
3350 	u8         indirect_table[0x18];
3351 
3352 	u8         rx_hash_fn[0x4];
3353 	u8         reserved_at_124[0x2];
3354 	u8         self_lb_block[0x2];
3355 	u8         transport_domain[0x18];
3356 
3357 	u8         rx_hash_toeplitz_key[10][0x20];
3358 
3359 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3360 
3361 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3362 
3363 	u8         reserved_at_2c0[0x4c0];
3364 };
3365 
3366 enum {
3367 	MLX5_SRQC_STATE_GOOD   = 0x0,
3368 	MLX5_SRQC_STATE_ERROR  = 0x1,
3369 };
3370 
3371 struct mlx5_ifc_srqc_bits {
3372 	u8         state[0x4];
3373 	u8         log_srq_size[0x4];
3374 	u8         reserved_at_8[0x18];
3375 
3376 	u8         wq_signature[0x1];
3377 	u8         cont_srq[0x1];
3378 	u8         reserved_at_22[0x1];
3379 	u8         rlky[0x1];
3380 	u8         reserved_at_24[0x1];
3381 	u8         log_rq_stride[0x3];
3382 	u8         xrcd[0x18];
3383 
3384 	u8         page_offset[0x6];
3385 	u8         reserved_at_46[0x2];
3386 	u8         cqn[0x18];
3387 
3388 	u8         reserved_at_60[0x20];
3389 
3390 	u8         reserved_at_80[0x2];
3391 	u8         log_page_size[0x6];
3392 	u8         reserved_at_88[0x18];
3393 
3394 	u8         reserved_at_a0[0x20];
3395 
3396 	u8         reserved_at_c0[0x8];
3397 	u8         pd[0x18];
3398 
3399 	u8         lwm[0x10];
3400 	u8         wqe_cnt[0x10];
3401 
3402 	u8         reserved_at_100[0x40];
3403 
3404 	u8         dbr_addr[0x40];
3405 
3406 	u8         reserved_at_180[0x80];
3407 };
3408 
3409 enum {
3410 	MLX5_SQC_STATE_RST  = 0x0,
3411 	MLX5_SQC_STATE_RDY  = 0x1,
3412 	MLX5_SQC_STATE_ERR  = 0x3,
3413 };
3414 
3415 struct mlx5_ifc_sqc_bits {
3416 	u8         rlky[0x1];
3417 	u8         cd_master[0x1];
3418 	u8         fre[0x1];
3419 	u8         flush_in_error_en[0x1];
3420 	u8         allow_multi_pkt_send_wqe[0x1];
3421 	u8	   min_wqe_inline_mode[0x3];
3422 	u8         state[0x4];
3423 	u8         reg_umr[0x1];
3424 	u8         allow_swp[0x1];
3425 	u8         hairpin[0x1];
3426 	u8         reserved_at_f[0xb];
3427 	u8	   ts_format[0x2];
3428 	u8	   reserved_at_1c[0x4];
3429 
3430 	u8         reserved_at_20[0x8];
3431 	u8         user_index[0x18];
3432 
3433 	u8         reserved_at_40[0x8];
3434 	u8         cqn[0x18];
3435 
3436 	u8         reserved_at_60[0x8];
3437 	u8         hairpin_peer_rq[0x18];
3438 
3439 	u8         reserved_at_80[0x10];
3440 	u8         hairpin_peer_vhca[0x10];
3441 
3442 	u8         reserved_at_a0[0x20];
3443 
3444 	u8         reserved_at_c0[0x8];
3445 	u8         ts_cqe_to_dest_cqn[0x18];
3446 
3447 	u8         reserved_at_e0[0x10];
3448 	u8         packet_pacing_rate_limit_index[0x10];
3449 	u8         tis_lst_sz[0x10];
3450 	u8         qos_queue_group_id[0x10];
3451 
3452 	u8         reserved_at_120[0x40];
3453 
3454 	u8         reserved_at_160[0x8];
3455 	u8         tis_num_0[0x18];
3456 
3457 	struct mlx5_ifc_wq_bits wq;
3458 };
3459 
3460 enum {
3461 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3462 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3463 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3464 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3465 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3466 };
3467 
3468 enum {
3469 	ELEMENT_TYPE_CAP_MASK_TASR		= 1 << 0,
3470 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
3471 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
3472 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
3473 };
3474 
3475 struct mlx5_ifc_scheduling_context_bits {
3476 	u8         element_type[0x8];
3477 	u8         reserved_at_8[0x18];
3478 
3479 	u8         element_attributes[0x20];
3480 
3481 	u8         parent_element_id[0x20];
3482 
3483 	u8         reserved_at_60[0x40];
3484 
3485 	u8         bw_share[0x20];
3486 
3487 	u8         max_average_bw[0x20];
3488 
3489 	u8         reserved_at_e0[0x120];
3490 };
3491 
3492 struct mlx5_ifc_rqtc_bits {
3493 	u8    reserved_at_0[0xa0];
3494 
3495 	u8    reserved_at_a0[0x5];
3496 	u8    list_q_type[0x3];
3497 	u8    reserved_at_a8[0x8];
3498 	u8    rqt_max_size[0x10];
3499 
3500 	u8    rq_vhca_id_format[0x1];
3501 	u8    reserved_at_c1[0xf];
3502 	u8    rqt_actual_size[0x10];
3503 
3504 	u8    reserved_at_e0[0x6a0];
3505 
3506 	struct mlx5_ifc_rq_num_bits rq_num[];
3507 };
3508 
3509 enum {
3510 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3511 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3512 };
3513 
3514 enum {
3515 	MLX5_RQC_STATE_RST  = 0x0,
3516 	MLX5_RQC_STATE_RDY  = 0x1,
3517 	MLX5_RQC_STATE_ERR  = 0x3,
3518 };
3519 
3520 struct mlx5_ifc_rqc_bits {
3521 	u8         rlky[0x1];
3522 	u8	   delay_drop_en[0x1];
3523 	u8         scatter_fcs[0x1];
3524 	u8         vsd[0x1];
3525 	u8         mem_rq_type[0x4];
3526 	u8         state[0x4];
3527 	u8         reserved_at_c[0x1];
3528 	u8         flush_in_error_en[0x1];
3529 	u8         hairpin[0x1];
3530 	u8         reserved_at_f[0xb];
3531 	u8	   ts_format[0x2];
3532 	u8	   reserved_at_1c[0x4];
3533 
3534 	u8         reserved_at_20[0x8];
3535 	u8         user_index[0x18];
3536 
3537 	u8         reserved_at_40[0x8];
3538 	u8         cqn[0x18];
3539 
3540 	u8         counter_set_id[0x8];
3541 	u8         reserved_at_68[0x18];
3542 
3543 	u8         reserved_at_80[0x8];
3544 	u8         rmpn[0x18];
3545 
3546 	u8         reserved_at_a0[0x8];
3547 	u8         hairpin_peer_sq[0x18];
3548 
3549 	u8         reserved_at_c0[0x10];
3550 	u8         hairpin_peer_vhca[0x10];
3551 
3552 	u8         reserved_at_e0[0xa0];
3553 
3554 	struct mlx5_ifc_wq_bits wq;
3555 };
3556 
3557 enum {
3558 	MLX5_RMPC_STATE_RDY  = 0x1,
3559 	MLX5_RMPC_STATE_ERR  = 0x3,
3560 };
3561 
3562 struct mlx5_ifc_rmpc_bits {
3563 	u8         reserved_at_0[0x8];
3564 	u8         state[0x4];
3565 	u8         reserved_at_c[0x14];
3566 
3567 	u8         basic_cyclic_rcv_wqe[0x1];
3568 	u8         reserved_at_21[0x1f];
3569 
3570 	u8         reserved_at_40[0x140];
3571 
3572 	struct mlx5_ifc_wq_bits wq;
3573 };
3574 
3575 struct mlx5_ifc_nic_vport_context_bits {
3576 	u8         reserved_at_0[0x5];
3577 	u8         min_wqe_inline_mode[0x3];
3578 	u8         reserved_at_8[0x15];
3579 	u8         disable_mc_local_lb[0x1];
3580 	u8         disable_uc_local_lb[0x1];
3581 	u8         roce_en[0x1];
3582 
3583 	u8         arm_change_event[0x1];
3584 	u8         reserved_at_21[0x1a];
3585 	u8         event_on_mtu[0x1];
3586 	u8         event_on_promisc_change[0x1];
3587 	u8         event_on_vlan_change[0x1];
3588 	u8         event_on_mc_address_change[0x1];
3589 	u8         event_on_uc_address_change[0x1];
3590 
3591 	u8         reserved_at_40[0xc];
3592 
3593 	u8	   affiliation_criteria[0x4];
3594 	u8	   affiliated_vhca_id[0x10];
3595 
3596 	u8	   reserved_at_60[0xd0];
3597 
3598 	u8         mtu[0x10];
3599 
3600 	u8         system_image_guid[0x40];
3601 	u8         port_guid[0x40];
3602 	u8         node_guid[0x40];
3603 
3604 	u8         reserved_at_200[0x140];
3605 	u8         qkey_violation_counter[0x10];
3606 	u8         reserved_at_350[0x430];
3607 
3608 	u8         promisc_uc[0x1];
3609 	u8         promisc_mc[0x1];
3610 	u8         promisc_all[0x1];
3611 	u8         reserved_at_783[0x2];
3612 	u8         allowed_list_type[0x3];
3613 	u8         reserved_at_788[0xc];
3614 	u8         allowed_list_size[0xc];
3615 
3616 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
3617 
3618 	u8         reserved_at_7e0[0x20];
3619 
3620 	u8         current_uc_mac_address[][0x40];
3621 };
3622 
3623 enum {
3624 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3625 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3626 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3627 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3628 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3629 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3630 };
3631 
3632 struct mlx5_ifc_mkc_bits {
3633 	u8         reserved_at_0[0x1];
3634 	u8         free[0x1];
3635 	u8         reserved_at_2[0x1];
3636 	u8         access_mode_4_2[0x3];
3637 	u8         reserved_at_6[0x7];
3638 	u8         relaxed_ordering_write[0x1];
3639 	u8         reserved_at_e[0x1];
3640 	u8         small_fence_on_rdma_read_response[0x1];
3641 	u8         umr_en[0x1];
3642 	u8         a[0x1];
3643 	u8         rw[0x1];
3644 	u8         rr[0x1];
3645 	u8         lw[0x1];
3646 	u8         lr[0x1];
3647 	u8         access_mode_1_0[0x2];
3648 	u8         reserved_at_18[0x8];
3649 
3650 	u8         qpn[0x18];
3651 	u8         mkey_7_0[0x8];
3652 
3653 	u8         reserved_at_40[0x20];
3654 
3655 	u8         length64[0x1];
3656 	u8         bsf_en[0x1];
3657 	u8         sync_umr[0x1];
3658 	u8         reserved_at_63[0x2];
3659 	u8         expected_sigerr_count[0x1];
3660 	u8         reserved_at_66[0x1];
3661 	u8         en_rinval[0x1];
3662 	u8         pd[0x18];
3663 
3664 	u8         start_addr[0x40];
3665 
3666 	u8         len[0x40];
3667 
3668 	u8         bsf_octword_size[0x20];
3669 
3670 	u8         reserved_at_120[0x80];
3671 
3672 	u8         translations_octword_size[0x20];
3673 
3674 	u8         reserved_at_1c0[0x19];
3675 	u8         relaxed_ordering_read[0x1];
3676 	u8         reserved_at_1d9[0x1];
3677 	u8         log_page_size[0x5];
3678 
3679 	u8         reserved_at_1e0[0x20];
3680 };
3681 
3682 struct mlx5_ifc_pkey_bits {
3683 	u8         reserved_at_0[0x10];
3684 	u8         pkey[0x10];
3685 };
3686 
3687 struct mlx5_ifc_array128_auto_bits {
3688 	u8         array128_auto[16][0x8];
3689 };
3690 
3691 struct mlx5_ifc_hca_vport_context_bits {
3692 	u8         field_select[0x20];
3693 
3694 	u8         reserved_at_20[0xe0];
3695 
3696 	u8         sm_virt_aware[0x1];
3697 	u8         has_smi[0x1];
3698 	u8         has_raw[0x1];
3699 	u8         grh_required[0x1];
3700 	u8         reserved_at_104[0xc];
3701 	u8         port_physical_state[0x4];
3702 	u8         vport_state_policy[0x4];
3703 	u8         port_state[0x4];
3704 	u8         vport_state[0x4];
3705 
3706 	u8         reserved_at_120[0x20];
3707 
3708 	u8         system_image_guid[0x40];
3709 
3710 	u8         port_guid[0x40];
3711 
3712 	u8         node_guid[0x40];
3713 
3714 	u8         cap_mask1[0x20];
3715 
3716 	u8         cap_mask1_field_select[0x20];
3717 
3718 	u8         cap_mask2[0x20];
3719 
3720 	u8         cap_mask2_field_select[0x20];
3721 
3722 	u8         reserved_at_280[0x80];
3723 
3724 	u8         lid[0x10];
3725 	u8         reserved_at_310[0x4];
3726 	u8         init_type_reply[0x4];
3727 	u8         lmc[0x3];
3728 	u8         subnet_timeout[0x5];
3729 
3730 	u8         sm_lid[0x10];
3731 	u8         sm_sl[0x4];
3732 	u8         reserved_at_334[0xc];
3733 
3734 	u8         qkey_violation_counter[0x10];
3735 	u8         pkey_violation_counter[0x10];
3736 
3737 	u8         reserved_at_360[0xca0];
3738 };
3739 
3740 struct mlx5_ifc_esw_vport_context_bits {
3741 	u8         fdb_to_vport_reg_c[0x1];
3742 	u8         reserved_at_1[0x2];
3743 	u8         vport_svlan_strip[0x1];
3744 	u8         vport_cvlan_strip[0x1];
3745 	u8         vport_svlan_insert[0x1];
3746 	u8         vport_cvlan_insert[0x2];
3747 	u8         fdb_to_vport_reg_c_id[0x8];
3748 	u8         reserved_at_10[0x10];
3749 
3750 	u8         reserved_at_20[0x20];
3751 
3752 	u8         svlan_cfi[0x1];
3753 	u8         svlan_pcp[0x3];
3754 	u8         svlan_id[0xc];
3755 	u8         cvlan_cfi[0x1];
3756 	u8         cvlan_pcp[0x3];
3757 	u8         cvlan_id[0xc];
3758 
3759 	u8         reserved_at_60[0x720];
3760 
3761 	u8         sw_steering_vport_icm_address_rx[0x40];
3762 
3763 	u8         sw_steering_vport_icm_address_tx[0x40];
3764 };
3765 
3766 enum {
3767 	MLX5_EQC_STATUS_OK                = 0x0,
3768 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3769 };
3770 
3771 enum {
3772 	MLX5_EQC_ST_ARMED  = 0x9,
3773 	MLX5_EQC_ST_FIRED  = 0xa,
3774 };
3775 
3776 struct mlx5_ifc_eqc_bits {
3777 	u8         status[0x4];
3778 	u8         reserved_at_4[0x9];
3779 	u8         ec[0x1];
3780 	u8         oi[0x1];
3781 	u8         reserved_at_f[0x5];
3782 	u8         st[0x4];
3783 	u8         reserved_at_18[0x8];
3784 
3785 	u8         reserved_at_20[0x20];
3786 
3787 	u8         reserved_at_40[0x14];
3788 	u8         page_offset[0x6];
3789 	u8         reserved_at_5a[0x6];
3790 
3791 	u8         reserved_at_60[0x3];
3792 	u8         log_eq_size[0x5];
3793 	u8         uar_page[0x18];
3794 
3795 	u8         reserved_at_80[0x20];
3796 
3797 	u8         reserved_at_a0[0x14];
3798 	u8         intr[0xc];
3799 
3800 	u8         reserved_at_c0[0x3];
3801 	u8         log_page_size[0x5];
3802 	u8         reserved_at_c8[0x18];
3803 
3804 	u8         reserved_at_e0[0x60];
3805 
3806 	u8         reserved_at_140[0x8];
3807 	u8         consumer_counter[0x18];
3808 
3809 	u8         reserved_at_160[0x8];
3810 	u8         producer_counter[0x18];
3811 
3812 	u8         reserved_at_180[0x80];
3813 };
3814 
3815 enum {
3816 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
3817 	MLX5_DCTC_STATE_DRAINING  = 0x1,
3818 	MLX5_DCTC_STATE_DRAINED   = 0x2,
3819 };
3820 
3821 enum {
3822 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3823 	MLX5_DCTC_CS_RES_NA         = 0x1,
3824 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3825 };
3826 
3827 enum {
3828 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
3829 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
3830 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3831 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3832 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3833 };
3834 
3835 struct mlx5_ifc_dctc_bits {
3836 	u8         reserved_at_0[0x4];
3837 	u8         state[0x4];
3838 	u8         reserved_at_8[0x18];
3839 
3840 	u8         reserved_at_20[0x8];
3841 	u8         user_index[0x18];
3842 
3843 	u8         reserved_at_40[0x8];
3844 	u8         cqn[0x18];
3845 
3846 	u8         counter_set_id[0x8];
3847 	u8         atomic_mode[0x4];
3848 	u8         rre[0x1];
3849 	u8         rwe[0x1];
3850 	u8         rae[0x1];
3851 	u8         atomic_like_write_en[0x1];
3852 	u8         latency_sensitive[0x1];
3853 	u8         rlky[0x1];
3854 	u8         free_ar[0x1];
3855 	u8         reserved_at_73[0xd];
3856 
3857 	u8         reserved_at_80[0x8];
3858 	u8         cs_res[0x8];
3859 	u8         reserved_at_90[0x3];
3860 	u8         min_rnr_nak[0x5];
3861 	u8         reserved_at_98[0x8];
3862 
3863 	u8         reserved_at_a0[0x8];
3864 	u8         srqn_xrqn[0x18];
3865 
3866 	u8         reserved_at_c0[0x8];
3867 	u8         pd[0x18];
3868 
3869 	u8         tclass[0x8];
3870 	u8         reserved_at_e8[0x4];
3871 	u8         flow_label[0x14];
3872 
3873 	u8         dc_access_key[0x40];
3874 
3875 	u8         reserved_at_140[0x5];
3876 	u8         mtu[0x3];
3877 	u8         port[0x8];
3878 	u8         pkey_index[0x10];
3879 
3880 	u8         reserved_at_160[0x8];
3881 	u8         my_addr_index[0x8];
3882 	u8         reserved_at_170[0x8];
3883 	u8         hop_limit[0x8];
3884 
3885 	u8         dc_access_key_violation_count[0x20];
3886 
3887 	u8         reserved_at_1a0[0x14];
3888 	u8         dei_cfi[0x1];
3889 	u8         eth_prio[0x3];
3890 	u8         ecn[0x2];
3891 	u8         dscp[0x6];
3892 
3893 	u8         reserved_at_1c0[0x20];
3894 	u8         ece[0x20];
3895 };
3896 
3897 enum {
3898 	MLX5_CQC_STATUS_OK             = 0x0,
3899 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3900 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3901 };
3902 
3903 enum {
3904 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3905 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3906 };
3907 
3908 enum {
3909 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3910 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3911 	MLX5_CQC_ST_FIRED                                 = 0xa,
3912 };
3913 
3914 enum {
3915 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3916 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3917 	MLX5_CQ_PERIOD_NUM_MODES
3918 };
3919 
3920 struct mlx5_ifc_cqc_bits {
3921 	u8         status[0x4];
3922 	u8         reserved_at_4[0x2];
3923 	u8         dbr_umem_valid[0x1];
3924 	u8         apu_cq[0x1];
3925 	u8         cqe_sz[0x3];
3926 	u8         cc[0x1];
3927 	u8         reserved_at_c[0x1];
3928 	u8         scqe_break_moderation_en[0x1];
3929 	u8         oi[0x1];
3930 	u8         cq_period_mode[0x2];
3931 	u8         cqe_comp_en[0x1];
3932 	u8         mini_cqe_res_format[0x2];
3933 	u8         st[0x4];
3934 	u8         reserved_at_18[0x8];
3935 
3936 	u8         reserved_at_20[0x20];
3937 
3938 	u8         reserved_at_40[0x14];
3939 	u8         page_offset[0x6];
3940 	u8         reserved_at_5a[0x6];
3941 
3942 	u8         reserved_at_60[0x3];
3943 	u8         log_cq_size[0x5];
3944 	u8         uar_page[0x18];
3945 
3946 	u8         reserved_at_80[0x4];
3947 	u8         cq_period[0xc];
3948 	u8         cq_max_count[0x10];
3949 
3950 	u8         c_eqn_or_apu_element[0x20];
3951 
3952 	u8         reserved_at_c0[0x3];
3953 	u8         log_page_size[0x5];
3954 	u8         reserved_at_c8[0x18];
3955 
3956 	u8         reserved_at_e0[0x20];
3957 
3958 	u8         reserved_at_100[0x8];
3959 	u8         last_notified_index[0x18];
3960 
3961 	u8         reserved_at_120[0x8];
3962 	u8         last_solicit_index[0x18];
3963 
3964 	u8         reserved_at_140[0x8];
3965 	u8         consumer_counter[0x18];
3966 
3967 	u8         reserved_at_160[0x8];
3968 	u8         producer_counter[0x18];
3969 
3970 	u8         reserved_at_180[0x40];
3971 
3972 	u8         dbr_addr[0x40];
3973 };
3974 
3975 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3976 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3977 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3978 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3979 	u8         reserved_at_0[0x800];
3980 };
3981 
3982 struct mlx5_ifc_query_adapter_param_block_bits {
3983 	u8         reserved_at_0[0xc0];
3984 
3985 	u8         reserved_at_c0[0x8];
3986 	u8         ieee_vendor_id[0x18];
3987 
3988 	u8         reserved_at_e0[0x10];
3989 	u8         vsd_vendor_id[0x10];
3990 
3991 	u8         vsd[208][0x8];
3992 
3993 	u8         vsd_contd_psid[16][0x8];
3994 };
3995 
3996 enum {
3997 	MLX5_XRQC_STATE_GOOD   = 0x0,
3998 	MLX5_XRQC_STATE_ERROR  = 0x1,
3999 };
4000 
4001 enum {
4002 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4003 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4004 };
4005 
4006 enum {
4007 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4008 };
4009 
4010 struct mlx5_ifc_tag_matching_topology_context_bits {
4011 	u8         log_matching_list_sz[0x4];
4012 	u8         reserved_at_4[0xc];
4013 	u8         append_next_index[0x10];
4014 
4015 	u8         sw_phase_cnt[0x10];
4016 	u8         hw_phase_cnt[0x10];
4017 
4018 	u8         reserved_at_40[0x40];
4019 };
4020 
4021 struct mlx5_ifc_xrqc_bits {
4022 	u8         state[0x4];
4023 	u8         rlkey[0x1];
4024 	u8         reserved_at_5[0xf];
4025 	u8         topology[0x4];
4026 	u8         reserved_at_18[0x4];
4027 	u8         offload[0x4];
4028 
4029 	u8         reserved_at_20[0x8];
4030 	u8         user_index[0x18];
4031 
4032 	u8         reserved_at_40[0x8];
4033 	u8         cqn[0x18];
4034 
4035 	u8         reserved_at_60[0xa0];
4036 
4037 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4038 
4039 	u8         reserved_at_180[0x280];
4040 
4041 	struct mlx5_ifc_wq_bits wq;
4042 };
4043 
4044 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4045 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4046 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4047 	u8         reserved_at_0[0x20];
4048 };
4049 
4050 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4051 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4052 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4053 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4054 	u8         reserved_at_0[0x20];
4055 };
4056 
4057 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4058 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4059 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4060 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4061 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4062 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4063 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4064 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4065 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4066 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4067 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4068 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4069 	u8         reserved_at_0[0x7c0];
4070 };
4071 
4072 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4073 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4074 	u8         reserved_at_0[0x7c0];
4075 };
4076 
4077 union mlx5_ifc_event_auto_bits {
4078 	struct mlx5_ifc_comp_event_bits comp_event;
4079 	struct mlx5_ifc_dct_events_bits dct_events;
4080 	struct mlx5_ifc_qp_events_bits qp_events;
4081 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4082 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4083 	struct mlx5_ifc_cq_error_bits cq_error;
4084 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4085 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4086 	struct mlx5_ifc_gpio_event_bits gpio_event;
4087 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4088 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4089 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4090 	u8         reserved_at_0[0xe0];
4091 };
4092 
4093 struct mlx5_ifc_health_buffer_bits {
4094 	u8         reserved_at_0[0x100];
4095 
4096 	u8         assert_existptr[0x20];
4097 
4098 	u8         assert_callra[0x20];
4099 
4100 	u8         reserved_at_140[0x40];
4101 
4102 	u8         fw_version[0x20];
4103 
4104 	u8         hw_id[0x20];
4105 
4106 	u8         reserved_at_1c0[0x20];
4107 
4108 	u8         irisc_index[0x8];
4109 	u8         synd[0x8];
4110 	u8         ext_synd[0x10];
4111 };
4112 
4113 struct mlx5_ifc_register_loopback_control_bits {
4114 	u8         no_lb[0x1];
4115 	u8         reserved_at_1[0x7];
4116 	u8         port[0x8];
4117 	u8         reserved_at_10[0x10];
4118 
4119 	u8         reserved_at_20[0x60];
4120 };
4121 
4122 struct mlx5_ifc_vport_tc_element_bits {
4123 	u8         traffic_class[0x4];
4124 	u8         reserved_at_4[0xc];
4125 	u8         vport_number[0x10];
4126 };
4127 
4128 struct mlx5_ifc_vport_element_bits {
4129 	u8         reserved_at_0[0x10];
4130 	u8         vport_number[0x10];
4131 };
4132 
4133 enum {
4134 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4135 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4136 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4137 };
4138 
4139 struct mlx5_ifc_tsar_element_bits {
4140 	u8         reserved_at_0[0x8];
4141 	u8         tsar_type[0x8];
4142 	u8         reserved_at_10[0x10];
4143 };
4144 
4145 enum {
4146 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4147 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4148 };
4149 
4150 struct mlx5_ifc_teardown_hca_out_bits {
4151 	u8         status[0x8];
4152 	u8         reserved_at_8[0x18];
4153 
4154 	u8         syndrome[0x20];
4155 
4156 	u8         reserved_at_40[0x3f];
4157 
4158 	u8         state[0x1];
4159 };
4160 
4161 enum {
4162 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4163 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4164 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4165 };
4166 
4167 struct mlx5_ifc_teardown_hca_in_bits {
4168 	u8         opcode[0x10];
4169 	u8         reserved_at_10[0x10];
4170 
4171 	u8         reserved_at_20[0x10];
4172 	u8         op_mod[0x10];
4173 
4174 	u8         reserved_at_40[0x10];
4175 	u8         profile[0x10];
4176 
4177 	u8         reserved_at_60[0x20];
4178 };
4179 
4180 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4181 	u8         status[0x8];
4182 	u8         reserved_at_8[0x18];
4183 
4184 	u8         syndrome[0x20];
4185 
4186 	u8         reserved_at_40[0x40];
4187 };
4188 
4189 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4190 	u8         opcode[0x10];
4191 	u8         uid[0x10];
4192 
4193 	u8         reserved_at_20[0x10];
4194 	u8         op_mod[0x10];
4195 
4196 	u8         reserved_at_40[0x8];
4197 	u8         qpn[0x18];
4198 
4199 	u8         reserved_at_60[0x20];
4200 
4201 	u8         opt_param_mask[0x20];
4202 
4203 	u8         reserved_at_a0[0x20];
4204 
4205 	struct mlx5_ifc_qpc_bits qpc;
4206 
4207 	u8         reserved_at_800[0x80];
4208 };
4209 
4210 struct mlx5_ifc_sqd2rts_qp_out_bits {
4211 	u8         status[0x8];
4212 	u8         reserved_at_8[0x18];
4213 
4214 	u8         syndrome[0x20];
4215 
4216 	u8         reserved_at_40[0x40];
4217 };
4218 
4219 struct mlx5_ifc_sqd2rts_qp_in_bits {
4220 	u8         opcode[0x10];
4221 	u8         uid[0x10];
4222 
4223 	u8         reserved_at_20[0x10];
4224 	u8         op_mod[0x10];
4225 
4226 	u8         reserved_at_40[0x8];
4227 	u8         qpn[0x18];
4228 
4229 	u8         reserved_at_60[0x20];
4230 
4231 	u8         opt_param_mask[0x20];
4232 
4233 	u8         reserved_at_a0[0x20];
4234 
4235 	struct mlx5_ifc_qpc_bits qpc;
4236 
4237 	u8         reserved_at_800[0x80];
4238 };
4239 
4240 struct mlx5_ifc_set_roce_address_out_bits {
4241 	u8         status[0x8];
4242 	u8         reserved_at_8[0x18];
4243 
4244 	u8         syndrome[0x20];
4245 
4246 	u8         reserved_at_40[0x40];
4247 };
4248 
4249 struct mlx5_ifc_set_roce_address_in_bits {
4250 	u8         opcode[0x10];
4251 	u8         reserved_at_10[0x10];
4252 
4253 	u8         reserved_at_20[0x10];
4254 	u8         op_mod[0x10];
4255 
4256 	u8         roce_address_index[0x10];
4257 	u8         reserved_at_50[0xc];
4258 	u8	   vhca_port_num[0x4];
4259 
4260 	u8         reserved_at_60[0x20];
4261 
4262 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4263 };
4264 
4265 struct mlx5_ifc_set_mad_demux_out_bits {
4266 	u8         status[0x8];
4267 	u8         reserved_at_8[0x18];
4268 
4269 	u8         syndrome[0x20];
4270 
4271 	u8         reserved_at_40[0x40];
4272 };
4273 
4274 enum {
4275 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4276 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4277 };
4278 
4279 struct mlx5_ifc_set_mad_demux_in_bits {
4280 	u8         opcode[0x10];
4281 	u8         reserved_at_10[0x10];
4282 
4283 	u8         reserved_at_20[0x10];
4284 	u8         op_mod[0x10];
4285 
4286 	u8         reserved_at_40[0x20];
4287 
4288 	u8         reserved_at_60[0x6];
4289 	u8         demux_mode[0x2];
4290 	u8         reserved_at_68[0x18];
4291 };
4292 
4293 struct mlx5_ifc_set_l2_table_entry_out_bits {
4294 	u8         status[0x8];
4295 	u8         reserved_at_8[0x18];
4296 
4297 	u8         syndrome[0x20];
4298 
4299 	u8         reserved_at_40[0x40];
4300 };
4301 
4302 struct mlx5_ifc_set_l2_table_entry_in_bits {
4303 	u8         opcode[0x10];
4304 	u8         reserved_at_10[0x10];
4305 
4306 	u8         reserved_at_20[0x10];
4307 	u8         op_mod[0x10];
4308 
4309 	u8         reserved_at_40[0x60];
4310 
4311 	u8         reserved_at_a0[0x8];
4312 	u8         table_index[0x18];
4313 
4314 	u8         reserved_at_c0[0x20];
4315 
4316 	u8         reserved_at_e0[0x13];
4317 	u8         vlan_valid[0x1];
4318 	u8         vlan[0xc];
4319 
4320 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4321 
4322 	u8         reserved_at_140[0xc0];
4323 };
4324 
4325 struct mlx5_ifc_set_issi_out_bits {
4326 	u8         status[0x8];
4327 	u8         reserved_at_8[0x18];
4328 
4329 	u8         syndrome[0x20];
4330 
4331 	u8         reserved_at_40[0x40];
4332 };
4333 
4334 struct mlx5_ifc_set_issi_in_bits {
4335 	u8         opcode[0x10];
4336 	u8         reserved_at_10[0x10];
4337 
4338 	u8         reserved_at_20[0x10];
4339 	u8         op_mod[0x10];
4340 
4341 	u8         reserved_at_40[0x10];
4342 	u8         current_issi[0x10];
4343 
4344 	u8         reserved_at_60[0x20];
4345 };
4346 
4347 struct mlx5_ifc_set_hca_cap_out_bits {
4348 	u8         status[0x8];
4349 	u8         reserved_at_8[0x18];
4350 
4351 	u8         syndrome[0x20];
4352 
4353 	u8         reserved_at_40[0x40];
4354 };
4355 
4356 struct mlx5_ifc_set_hca_cap_in_bits {
4357 	u8         opcode[0x10];
4358 	u8         reserved_at_10[0x10];
4359 
4360 	u8         reserved_at_20[0x10];
4361 	u8         op_mod[0x10];
4362 
4363 	u8         other_function[0x1];
4364 	u8         reserved_at_41[0xf];
4365 	u8         function_id[0x10];
4366 
4367 	u8         reserved_at_60[0x20];
4368 
4369 	union mlx5_ifc_hca_cap_union_bits capability;
4370 };
4371 
4372 enum {
4373 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4374 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4375 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4376 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4377 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4378 };
4379 
4380 struct mlx5_ifc_set_fte_out_bits {
4381 	u8         status[0x8];
4382 	u8         reserved_at_8[0x18];
4383 
4384 	u8         syndrome[0x20];
4385 
4386 	u8         reserved_at_40[0x40];
4387 };
4388 
4389 struct mlx5_ifc_set_fte_in_bits {
4390 	u8         opcode[0x10];
4391 	u8         reserved_at_10[0x10];
4392 
4393 	u8         reserved_at_20[0x10];
4394 	u8         op_mod[0x10];
4395 
4396 	u8         other_vport[0x1];
4397 	u8         reserved_at_41[0xf];
4398 	u8         vport_number[0x10];
4399 
4400 	u8         reserved_at_60[0x20];
4401 
4402 	u8         table_type[0x8];
4403 	u8         reserved_at_88[0x18];
4404 
4405 	u8         reserved_at_a0[0x8];
4406 	u8         table_id[0x18];
4407 
4408 	u8         ignore_flow_level[0x1];
4409 	u8         reserved_at_c1[0x17];
4410 	u8         modify_enable_mask[0x8];
4411 
4412 	u8         reserved_at_e0[0x20];
4413 
4414 	u8         flow_index[0x20];
4415 
4416 	u8         reserved_at_120[0xe0];
4417 
4418 	struct mlx5_ifc_flow_context_bits flow_context;
4419 };
4420 
4421 struct mlx5_ifc_rts2rts_qp_out_bits {
4422 	u8         status[0x8];
4423 	u8         reserved_at_8[0x18];
4424 
4425 	u8         syndrome[0x20];
4426 
4427 	u8         reserved_at_40[0x20];
4428 	u8         ece[0x20];
4429 };
4430 
4431 struct mlx5_ifc_rts2rts_qp_in_bits {
4432 	u8         opcode[0x10];
4433 	u8         uid[0x10];
4434 
4435 	u8         reserved_at_20[0x10];
4436 	u8         op_mod[0x10];
4437 
4438 	u8         reserved_at_40[0x8];
4439 	u8         qpn[0x18];
4440 
4441 	u8         reserved_at_60[0x20];
4442 
4443 	u8         opt_param_mask[0x20];
4444 
4445 	u8         ece[0x20];
4446 
4447 	struct mlx5_ifc_qpc_bits qpc;
4448 
4449 	u8         reserved_at_800[0x80];
4450 };
4451 
4452 struct mlx5_ifc_rtr2rts_qp_out_bits {
4453 	u8         status[0x8];
4454 	u8         reserved_at_8[0x18];
4455 
4456 	u8         syndrome[0x20];
4457 
4458 	u8         reserved_at_40[0x20];
4459 	u8         ece[0x20];
4460 };
4461 
4462 struct mlx5_ifc_rtr2rts_qp_in_bits {
4463 	u8         opcode[0x10];
4464 	u8         uid[0x10];
4465 
4466 	u8         reserved_at_20[0x10];
4467 	u8         op_mod[0x10];
4468 
4469 	u8         reserved_at_40[0x8];
4470 	u8         qpn[0x18];
4471 
4472 	u8         reserved_at_60[0x20];
4473 
4474 	u8         opt_param_mask[0x20];
4475 
4476 	u8         ece[0x20];
4477 
4478 	struct mlx5_ifc_qpc_bits qpc;
4479 
4480 	u8         reserved_at_800[0x80];
4481 };
4482 
4483 struct mlx5_ifc_rst2init_qp_out_bits {
4484 	u8         status[0x8];
4485 	u8         reserved_at_8[0x18];
4486 
4487 	u8         syndrome[0x20];
4488 
4489 	u8         reserved_at_40[0x20];
4490 	u8         ece[0x20];
4491 };
4492 
4493 struct mlx5_ifc_rst2init_qp_in_bits {
4494 	u8         opcode[0x10];
4495 	u8         uid[0x10];
4496 
4497 	u8         reserved_at_20[0x10];
4498 	u8         op_mod[0x10];
4499 
4500 	u8         reserved_at_40[0x8];
4501 	u8         qpn[0x18];
4502 
4503 	u8         reserved_at_60[0x20];
4504 
4505 	u8         opt_param_mask[0x20];
4506 
4507 	u8         ece[0x20];
4508 
4509 	struct mlx5_ifc_qpc_bits qpc;
4510 
4511 	u8         reserved_at_800[0x80];
4512 };
4513 
4514 struct mlx5_ifc_query_xrq_out_bits {
4515 	u8         status[0x8];
4516 	u8         reserved_at_8[0x18];
4517 
4518 	u8         syndrome[0x20];
4519 
4520 	u8         reserved_at_40[0x40];
4521 
4522 	struct mlx5_ifc_xrqc_bits xrq_context;
4523 };
4524 
4525 struct mlx5_ifc_query_xrq_in_bits {
4526 	u8         opcode[0x10];
4527 	u8         reserved_at_10[0x10];
4528 
4529 	u8         reserved_at_20[0x10];
4530 	u8         op_mod[0x10];
4531 
4532 	u8         reserved_at_40[0x8];
4533 	u8         xrqn[0x18];
4534 
4535 	u8         reserved_at_60[0x20];
4536 };
4537 
4538 struct mlx5_ifc_query_xrc_srq_out_bits {
4539 	u8         status[0x8];
4540 	u8         reserved_at_8[0x18];
4541 
4542 	u8         syndrome[0x20];
4543 
4544 	u8         reserved_at_40[0x40];
4545 
4546 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4547 
4548 	u8         reserved_at_280[0x600];
4549 
4550 	u8         pas[][0x40];
4551 };
4552 
4553 struct mlx5_ifc_query_xrc_srq_in_bits {
4554 	u8         opcode[0x10];
4555 	u8         reserved_at_10[0x10];
4556 
4557 	u8         reserved_at_20[0x10];
4558 	u8         op_mod[0x10];
4559 
4560 	u8         reserved_at_40[0x8];
4561 	u8         xrc_srqn[0x18];
4562 
4563 	u8         reserved_at_60[0x20];
4564 };
4565 
4566 enum {
4567 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4568 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4569 };
4570 
4571 struct mlx5_ifc_query_vport_state_out_bits {
4572 	u8         status[0x8];
4573 	u8         reserved_at_8[0x18];
4574 
4575 	u8         syndrome[0x20];
4576 
4577 	u8         reserved_at_40[0x20];
4578 
4579 	u8         reserved_at_60[0x18];
4580 	u8         admin_state[0x4];
4581 	u8         state[0x4];
4582 };
4583 
4584 enum {
4585 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4586 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4587 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4588 };
4589 
4590 struct mlx5_ifc_arm_monitor_counter_in_bits {
4591 	u8         opcode[0x10];
4592 	u8         uid[0x10];
4593 
4594 	u8         reserved_at_20[0x10];
4595 	u8         op_mod[0x10];
4596 
4597 	u8         reserved_at_40[0x20];
4598 
4599 	u8         reserved_at_60[0x20];
4600 };
4601 
4602 struct mlx5_ifc_arm_monitor_counter_out_bits {
4603 	u8         status[0x8];
4604 	u8         reserved_at_8[0x18];
4605 
4606 	u8         syndrome[0x20];
4607 
4608 	u8         reserved_at_40[0x40];
4609 };
4610 
4611 enum {
4612 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4613 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4614 };
4615 
4616 enum mlx5_monitor_counter_ppcnt {
4617 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4618 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4619 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4620 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4621 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4622 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4623 };
4624 
4625 enum {
4626 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4627 };
4628 
4629 struct mlx5_ifc_monitor_counter_output_bits {
4630 	u8         reserved_at_0[0x4];
4631 	u8         type[0x4];
4632 	u8         reserved_at_8[0x8];
4633 	u8         counter[0x10];
4634 
4635 	u8         counter_group_id[0x20];
4636 };
4637 
4638 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4639 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4640 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4641 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4642 
4643 struct mlx5_ifc_set_monitor_counter_in_bits {
4644 	u8         opcode[0x10];
4645 	u8         uid[0x10];
4646 
4647 	u8         reserved_at_20[0x10];
4648 	u8         op_mod[0x10];
4649 
4650 	u8         reserved_at_40[0x10];
4651 	u8         num_of_counters[0x10];
4652 
4653 	u8         reserved_at_60[0x20];
4654 
4655 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4656 };
4657 
4658 struct mlx5_ifc_set_monitor_counter_out_bits {
4659 	u8         status[0x8];
4660 	u8         reserved_at_8[0x18];
4661 
4662 	u8         syndrome[0x20];
4663 
4664 	u8         reserved_at_40[0x40];
4665 };
4666 
4667 struct mlx5_ifc_query_vport_state_in_bits {
4668 	u8         opcode[0x10];
4669 	u8         reserved_at_10[0x10];
4670 
4671 	u8         reserved_at_20[0x10];
4672 	u8         op_mod[0x10];
4673 
4674 	u8         other_vport[0x1];
4675 	u8         reserved_at_41[0xf];
4676 	u8         vport_number[0x10];
4677 
4678 	u8         reserved_at_60[0x20];
4679 };
4680 
4681 struct mlx5_ifc_query_vnic_env_out_bits {
4682 	u8         status[0x8];
4683 	u8         reserved_at_8[0x18];
4684 
4685 	u8         syndrome[0x20];
4686 
4687 	u8         reserved_at_40[0x40];
4688 
4689 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4690 };
4691 
4692 enum {
4693 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4694 };
4695 
4696 struct mlx5_ifc_query_vnic_env_in_bits {
4697 	u8         opcode[0x10];
4698 	u8         reserved_at_10[0x10];
4699 
4700 	u8         reserved_at_20[0x10];
4701 	u8         op_mod[0x10];
4702 
4703 	u8         other_vport[0x1];
4704 	u8         reserved_at_41[0xf];
4705 	u8         vport_number[0x10];
4706 
4707 	u8         reserved_at_60[0x20];
4708 };
4709 
4710 struct mlx5_ifc_query_vport_counter_out_bits {
4711 	u8         status[0x8];
4712 	u8         reserved_at_8[0x18];
4713 
4714 	u8         syndrome[0x20];
4715 
4716 	u8         reserved_at_40[0x40];
4717 
4718 	struct mlx5_ifc_traffic_counter_bits received_errors;
4719 
4720 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
4721 
4722 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4723 
4724 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4725 
4726 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4727 
4728 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4729 
4730 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4731 
4732 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4733 
4734 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4735 
4736 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4737 
4738 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4739 
4740 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4741 
4742 	u8         reserved_at_680[0xa00];
4743 };
4744 
4745 enum {
4746 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4747 };
4748 
4749 struct mlx5_ifc_query_vport_counter_in_bits {
4750 	u8         opcode[0x10];
4751 	u8         reserved_at_10[0x10];
4752 
4753 	u8         reserved_at_20[0x10];
4754 	u8         op_mod[0x10];
4755 
4756 	u8         other_vport[0x1];
4757 	u8         reserved_at_41[0xb];
4758 	u8	   port_num[0x4];
4759 	u8         vport_number[0x10];
4760 
4761 	u8         reserved_at_60[0x60];
4762 
4763 	u8         clear[0x1];
4764 	u8         reserved_at_c1[0x1f];
4765 
4766 	u8         reserved_at_e0[0x20];
4767 };
4768 
4769 struct mlx5_ifc_query_tis_out_bits {
4770 	u8         status[0x8];
4771 	u8         reserved_at_8[0x18];
4772 
4773 	u8         syndrome[0x20];
4774 
4775 	u8         reserved_at_40[0x40];
4776 
4777 	struct mlx5_ifc_tisc_bits tis_context;
4778 };
4779 
4780 struct mlx5_ifc_query_tis_in_bits {
4781 	u8         opcode[0x10];
4782 	u8         reserved_at_10[0x10];
4783 
4784 	u8         reserved_at_20[0x10];
4785 	u8         op_mod[0x10];
4786 
4787 	u8         reserved_at_40[0x8];
4788 	u8         tisn[0x18];
4789 
4790 	u8         reserved_at_60[0x20];
4791 };
4792 
4793 struct mlx5_ifc_query_tir_out_bits {
4794 	u8         status[0x8];
4795 	u8         reserved_at_8[0x18];
4796 
4797 	u8         syndrome[0x20];
4798 
4799 	u8         reserved_at_40[0xc0];
4800 
4801 	struct mlx5_ifc_tirc_bits tir_context;
4802 };
4803 
4804 struct mlx5_ifc_query_tir_in_bits {
4805 	u8         opcode[0x10];
4806 	u8         reserved_at_10[0x10];
4807 
4808 	u8         reserved_at_20[0x10];
4809 	u8         op_mod[0x10];
4810 
4811 	u8         reserved_at_40[0x8];
4812 	u8         tirn[0x18];
4813 
4814 	u8         reserved_at_60[0x20];
4815 };
4816 
4817 struct mlx5_ifc_query_srq_out_bits {
4818 	u8         status[0x8];
4819 	u8         reserved_at_8[0x18];
4820 
4821 	u8         syndrome[0x20];
4822 
4823 	u8         reserved_at_40[0x40];
4824 
4825 	struct mlx5_ifc_srqc_bits srq_context_entry;
4826 
4827 	u8         reserved_at_280[0x600];
4828 
4829 	u8         pas[][0x40];
4830 };
4831 
4832 struct mlx5_ifc_query_srq_in_bits {
4833 	u8         opcode[0x10];
4834 	u8         reserved_at_10[0x10];
4835 
4836 	u8         reserved_at_20[0x10];
4837 	u8         op_mod[0x10];
4838 
4839 	u8         reserved_at_40[0x8];
4840 	u8         srqn[0x18];
4841 
4842 	u8         reserved_at_60[0x20];
4843 };
4844 
4845 struct mlx5_ifc_query_sq_out_bits {
4846 	u8         status[0x8];
4847 	u8         reserved_at_8[0x18];
4848 
4849 	u8         syndrome[0x20];
4850 
4851 	u8         reserved_at_40[0xc0];
4852 
4853 	struct mlx5_ifc_sqc_bits sq_context;
4854 };
4855 
4856 struct mlx5_ifc_query_sq_in_bits {
4857 	u8         opcode[0x10];
4858 	u8         reserved_at_10[0x10];
4859 
4860 	u8         reserved_at_20[0x10];
4861 	u8         op_mod[0x10];
4862 
4863 	u8         reserved_at_40[0x8];
4864 	u8         sqn[0x18];
4865 
4866 	u8         reserved_at_60[0x20];
4867 };
4868 
4869 struct mlx5_ifc_query_special_contexts_out_bits {
4870 	u8         status[0x8];
4871 	u8         reserved_at_8[0x18];
4872 
4873 	u8         syndrome[0x20];
4874 
4875 	u8         dump_fill_mkey[0x20];
4876 
4877 	u8         resd_lkey[0x20];
4878 
4879 	u8         null_mkey[0x20];
4880 
4881 	u8         reserved_at_a0[0x60];
4882 };
4883 
4884 struct mlx5_ifc_query_special_contexts_in_bits {
4885 	u8         opcode[0x10];
4886 	u8         reserved_at_10[0x10];
4887 
4888 	u8         reserved_at_20[0x10];
4889 	u8         op_mod[0x10];
4890 
4891 	u8         reserved_at_40[0x40];
4892 };
4893 
4894 struct mlx5_ifc_query_scheduling_element_out_bits {
4895 	u8         opcode[0x10];
4896 	u8         reserved_at_10[0x10];
4897 
4898 	u8         reserved_at_20[0x10];
4899 	u8         op_mod[0x10];
4900 
4901 	u8         reserved_at_40[0xc0];
4902 
4903 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
4904 
4905 	u8         reserved_at_300[0x100];
4906 };
4907 
4908 enum {
4909 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4910 	SCHEDULING_HIERARCHY_NIC = 0x3,
4911 };
4912 
4913 struct mlx5_ifc_query_scheduling_element_in_bits {
4914 	u8         opcode[0x10];
4915 	u8         reserved_at_10[0x10];
4916 
4917 	u8         reserved_at_20[0x10];
4918 	u8         op_mod[0x10];
4919 
4920 	u8         scheduling_hierarchy[0x8];
4921 	u8         reserved_at_48[0x18];
4922 
4923 	u8         scheduling_element_id[0x20];
4924 
4925 	u8         reserved_at_80[0x180];
4926 };
4927 
4928 struct mlx5_ifc_query_rqt_out_bits {
4929 	u8         status[0x8];
4930 	u8         reserved_at_8[0x18];
4931 
4932 	u8         syndrome[0x20];
4933 
4934 	u8         reserved_at_40[0xc0];
4935 
4936 	struct mlx5_ifc_rqtc_bits rqt_context;
4937 };
4938 
4939 struct mlx5_ifc_query_rqt_in_bits {
4940 	u8         opcode[0x10];
4941 	u8         reserved_at_10[0x10];
4942 
4943 	u8         reserved_at_20[0x10];
4944 	u8         op_mod[0x10];
4945 
4946 	u8         reserved_at_40[0x8];
4947 	u8         rqtn[0x18];
4948 
4949 	u8         reserved_at_60[0x20];
4950 };
4951 
4952 struct mlx5_ifc_query_rq_out_bits {
4953 	u8         status[0x8];
4954 	u8         reserved_at_8[0x18];
4955 
4956 	u8         syndrome[0x20];
4957 
4958 	u8         reserved_at_40[0xc0];
4959 
4960 	struct mlx5_ifc_rqc_bits rq_context;
4961 };
4962 
4963 struct mlx5_ifc_query_rq_in_bits {
4964 	u8         opcode[0x10];
4965 	u8         reserved_at_10[0x10];
4966 
4967 	u8         reserved_at_20[0x10];
4968 	u8         op_mod[0x10];
4969 
4970 	u8         reserved_at_40[0x8];
4971 	u8         rqn[0x18];
4972 
4973 	u8         reserved_at_60[0x20];
4974 };
4975 
4976 struct mlx5_ifc_query_roce_address_out_bits {
4977 	u8         status[0x8];
4978 	u8         reserved_at_8[0x18];
4979 
4980 	u8         syndrome[0x20];
4981 
4982 	u8         reserved_at_40[0x40];
4983 
4984 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4985 };
4986 
4987 struct mlx5_ifc_query_roce_address_in_bits {
4988 	u8         opcode[0x10];
4989 	u8         reserved_at_10[0x10];
4990 
4991 	u8         reserved_at_20[0x10];
4992 	u8         op_mod[0x10];
4993 
4994 	u8         roce_address_index[0x10];
4995 	u8         reserved_at_50[0xc];
4996 	u8	   vhca_port_num[0x4];
4997 
4998 	u8         reserved_at_60[0x20];
4999 };
5000 
5001 struct mlx5_ifc_query_rmp_out_bits {
5002 	u8         status[0x8];
5003 	u8         reserved_at_8[0x18];
5004 
5005 	u8         syndrome[0x20];
5006 
5007 	u8         reserved_at_40[0xc0];
5008 
5009 	struct mlx5_ifc_rmpc_bits rmp_context;
5010 };
5011 
5012 struct mlx5_ifc_query_rmp_in_bits {
5013 	u8         opcode[0x10];
5014 	u8         reserved_at_10[0x10];
5015 
5016 	u8         reserved_at_20[0x10];
5017 	u8         op_mod[0x10];
5018 
5019 	u8         reserved_at_40[0x8];
5020 	u8         rmpn[0x18];
5021 
5022 	u8         reserved_at_60[0x20];
5023 };
5024 
5025 struct mlx5_ifc_query_qp_out_bits {
5026 	u8         status[0x8];
5027 	u8         reserved_at_8[0x18];
5028 
5029 	u8         syndrome[0x20];
5030 
5031 	u8         reserved_at_40[0x20];
5032 	u8         ece[0x20];
5033 
5034 	u8         opt_param_mask[0x20];
5035 
5036 	u8         reserved_at_a0[0x20];
5037 
5038 	struct mlx5_ifc_qpc_bits qpc;
5039 
5040 	u8         reserved_at_800[0x80];
5041 
5042 	u8         pas[][0x40];
5043 };
5044 
5045 struct mlx5_ifc_query_qp_in_bits {
5046 	u8         opcode[0x10];
5047 	u8         reserved_at_10[0x10];
5048 
5049 	u8         reserved_at_20[0x10];
5050 	u8         op_mod[0x10];
5051 
5052 	u8         reserved_at_40[0x8];
5053 	u8         qpn[0x18];
5054 
5055 	u8         reserved_at_60[0x20];
5056 };
5057 
5058 struct mlx5_ifc_query_q_counter_out_bits {
5059 	u8         status[0x8];
5060 	u8         reserved_at_8[0x18];
5061 
5062 	u8         syndrome[0x20];
5063 
5064 	u8         reserved_at_40[0x40];
5065 
5066 	u8         rx_write_requests[0x20];
5067 
5068 	u8         reserved_at_a0[0x20];
5069 
5070 	u8         rx_read_requests[0x20];
5071 
5072 	u8         reserved_at_e0[0x20];
5073 
5074 	u8         rx_atomic_requests[0x20];
5075 
5076 	u8         reserved_at_120[0x20];
5077 
5078 	u8         rx_dct_connect[0x20];
5079 
5080 	u8         reserved_at_160[0x20];
5081 
5082 	u8         out_of_buffer[0x20];
5083 
5084 	u8         reserved_at_1a0[0x20];
5085 
5086 	u8         out_of_sequence[0x20];
5087 
5088 	u8         reserved_at_1e0[0x20];
5089 
5090 	u8         duplicate_request[0x20];
5091 
5092 	u8         reserved_at_220[0x20];
5093 
5094 	u8         rnr_nak_retry_err[0x20];
5095 
5096 	u8         reserved_at_260[0x20];
5097 
5098 	u8         packet_seq_err[0x20];
5099 
5100 	u8         reserved_at_2a0[0x20];
5101 
5102 	u8         implied_nak_seq_err[0x20];
5103 
5104 	u8         reserved_at_2e0[0x20];
5105 
5106 	u8         local_ack_timeout_err[0x20];
5107 
5108 	u8         reserved_at_320[0xa0];
5109 
5110 	u8         resp_local_length_error[0x20];
5111 
5112 	u8         req_local_length_error[0x20];
5113 
5114 	u8         resp_local_qp_error[0x20];
5115 
5116 	u8         local_operation_error[0x20];
5117 
5118 	u8         resp_local_protection[0x20];
5119 
5120 	u8         req_local_protection[0x20];
5121 
5122 	u8         resp_cqe_error[0x20];
5123 
5124 	u8         req_cqe_error[0x20];
5125 
5126 	u8         req_mw_binding[0x20];
5127 
5128 	u8         req_bad_response[0x20];
5129 
5130 	u8         req_remote_invalid_request[0x20];
5131 
5132 	u8         resp_remote_invalid_request[0x20];
5133 
5134 	u8         req_remote_access_errors[0x20];
5135 
5136 	u8	   resp_remote_access_errors[0x20];
5137 
5138 	u8         req_remote_operation_errors[0x20];
5139 
5140 	u8         req_transport_retries_exceeded[0x20];
5141 
5142 	u8         cq_overflow[0x20];
5143 
5144 	u8         resp_cqe_flush_error[0x20];
5145 
5146 	u8         req_cqe_flush_error[0x20];
5147 
5148 	u8         reserved_at_620[0x20];
5149 
5150 	u8         roce_adp_retrans[0x20];
5151 
5152 	u8         roce_adp_retrans_to[0x20];
5153 
5154 	u8         roce_slow_restart[0x20];
5155 
5156 	u8         roce_slow_restart_cnps[0x20];
5157 
5158 	u8         roce_slow_restart_trans[0x20];
5159 
5160 	u8         reserved_at_6e0[0x120];
5161 };
5162 
5163 struct mlx5_ifc_query_q_counter_in_bits {
5164 	u8         opcode[0x10];
5165 	u8         reserved_at_10[0x10];
5166 
5167 	u8         reserved_at_20[0x10];
5168 	u8         op_mod[0x10];
5169 
5170 	u8         reserved_at_40[0x80];
5171 
5172 	u8         clear[0x1];
5173 	u8         reserved_at_c1[0x1f];
5174 
5175 	u8         reserved_at_e0[0x18];
5176 	u8         counter_set_id[0x8];
5177 };
5178 
5179 struct mlx5_ifc_query_pages_out_bits {
5180 	u8         status[0x8];
5181 	u8         reserved_at_8[0x18];
5182 
5183 	u8         syndrome[0x20];
5184 
5185 	u8         embedded_cpu_function[0x1];
5186 	u8         reserved_at_41[0xf];
5187 	u8         function_id[0x10];
5188 
5189 	u8         num_pages[0x20];
5190 };
5191 
5192 enum {
5193 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5194 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5195 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5196 };
5197 
5198 struct mlx5_ifc_query_pages_in_bits {
5199 	u8         opcode[0x10];
5200 	u8         reserved_at_10[0x10];
5201 
5202 	u8         reserved_at_20[0x10];
5203 	u8         op_mod[0x10];
5204 
5205 	u8         embedded_cpu_function[0x1];
5206 	u8         reserved_at_41[0xf];
5207 	u8         function_id[0x10];
5208 
5209 	u8         reserved_at_60[0x20];
5210 };
5211 
5212 struct mlx5_ifc_query_nic_vport_context_out_bits {
5213 	u8         status[0x8];
5214 	u8         reserved_at_8[0x18];
5215 
5216 	u8         syndrome[0x20];
5217 
5218 	u8         reserved_at_40[0x40];
5219 
5220 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5221 };
5222 
5223 struct mlx5_ifc_query_nic_vport_context_in_bits {
5224 	u8         opcode[0x10];
5225 	u8         reserved_at_10[0x10];
5226 
5227 	u8         reserved_at_20[0x10];
5228 	u8         op_mod[0x10];
5229 
5230 	u8         other_vport[0x1];
5231 	u8         reserved_at_41[0xf];
5232 	u8         vport_number[0x10];
5233 
5234 	u8         reserved_at_60[0x5];
5235 	u8         allowed_list_type[0x3];
5236 	u8         reserved_at_68[0x18];
5237 };
5238 
5239 struct mlx5_ifc_query_mkey_out_bits {
5240 	u8         status[0x8];
5241 	u8         reserved_at_8[0x18];
5242 
5243 	u8         syndrome[0x20];
5244 
5245 	u8         reserved_at_40[0x40];
5246 
5247 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5248 
5249 	u8         reserved_at_280[0x600];
5250 
5251 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5252 
5253 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5254 };
5255 
5256 struct mlx5_ifc_query_mkey_in_bits {
5257 	u8         opcode[0x10];
5258 	u8         reserved_at_10[0x10];
5259 
5260 	u8         reserved_at_20[0x10];
5261 	u8         op_mod[0x10];
5262 
5263 	u8         reserved_at_40[0x8];
5264 	u8         mkey_index[0x18];
5265 
5266 	u8         pg_access[0x1];
5267 	u8         reserved_at_61[0x1f];
5268 };
5269 
5270 struct mlx5_ifc_query_mad_demux_out_bits {
5271 	u8         status[0x8];
5272 	u8         reserved_at_8[0x18];
5273 
5274 	u8         syndrome[0x20];
5275 
5276 	u8         reserved_at_40[0x40];
5277 
5278 	u8         mad_dumux_parameters_block[0x20];
5279 };
5280 
5281 struct mlx5_ifc_query_mad_demux_in_bits {
5282 	u8         opcode[0x10];
5283 	u8         reserved_at_10[0x10];
5284 
5285 	u8         reserved_at_20[0x10];
5286 	u8         op_mod[0x10];
5287 
5288 	u8         reserved_at_40[0x40];
5289 };
5290 
5291 struct mlx5_ifc_query_l2_table_entry_out_bits {
5292 	u8         status[0x8];
5293 	u8         reserved_at_8[0x18];
5294 
5295 	u8         syndrome[0x20];
5296 
5297 	u8         reserved_at_40[0xa0];
5298 
5299 	u8         reserved_at_e0[0x13];
5300 	u8         vlan_valid[0x1];
5301 	u8         vlan[0xc];
5302 
5303 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5304 
5305 	u8         reserved_at_140[0xc0];
5306 };
5307 
5308 struct mlx5_ifc_query_l2_table_entry_in_bits {
5309 	u8         opcode[0x10];
5310 	u8         reserved_at_10[0x10];
5311 
5312 	u8         reserved_at_20[0x10];
5313 	u8         op_mod[0x10];
5314 
5315 	u8         reserved_at_40[0x60];
5316 
5317 	u8         reserved_at_a0[0x8];
5318 	u8         table_index[0x18];
5319 
5320 	u8         reserved_at_c0[0x140];
5321 };
5322 
5323 struct mlx5_ifc_query_issi_out_bits {
5324 	u8         status[0x8];
5325 	u8         reserved_at_8[0x18];
5326 
5327 	u8         syndrome[0x20];
5328 
5329 	u8         reserved_at_40[0x10];
5330 	u8         current_issi[0x10];
5331 
5332 	u8         reserved_at_60[0xa0];
5333 
5334 	u8         reserved_at_100[76][0x8];
5335 	u8         supported_issi_dw0[0x20];
5336 };
5337 
5338 struct mlx5_ifc_query_issi_in_bits {
5339 	u8         opcode[0x10];
5340 	u8         reserved_at_10[0x10];
5341 
5342 	u8         reserved_at_20[0x10];
5343 	u8         op_mod[0x10];
5344 
5345 	u8         reserved_at_40[0x40];
5346 };
5347 
5348 struct mlx5_ifc_set_driver_version_out_bits {
5349 	u8         status[0x8];
5350 	u8         reserved_0[0x18];
5351 
5352 	u8         syndrome[0x20];
5353 	u8         reserved_1[0x40];
5354 };
5355 
5356 struct mlx5_ifc_set_driver_version_in_bits {
5357 	u8         opcode[0x10];
5358 	u8         reserved_0[0x10];
5359 
5360 	u8         reserved_1[0x10];
5361 	u8         op_mod[0x10];
5362 
5363 	u8         reserved_2[0x40];
5364 	u8         driver_version[64][0x8];
5365 };
5366 
5367 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5368 	u8         status[0x8];
5369 	u8         reserved_at_8[0x18];
5370 
5371 	u8         syndrome[0x20];
5372 
5373 	u8         reserved_at_40[0x40];
5374 
5375 	struct mlx5_ifc_pkey_bits pkey[];
5376 };
5377 
5378 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5379 	u8         opcode[0x10];
5380 	u8         reserved_at_10[0x10];
5381 
5382 	u8         reserved_at_20[0x10];
5383 	u8         op_mod[0x10];
5384 
5385 	u8         other_vport[0x1];
5386 	u8         reserved_at_41[0xb];
5387 	u8         port_num[0x4];
5388 	u8         vport_number[0x10];
5389 
5390 	u8         reserved_at_60[0x10];
5391 	u8         pkey_index[0x10];
5392 };
5393 
5394 enum {
5395 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
5396 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
5397 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
5398 };
5399 
5400 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5401 	u8         status[0x8];
5402 	u8         reserved_at_8[0x18];
5403 
5404 	u8         syndrome[0x20];
5405 
5406 	u8         reserved_at_40[0x20];
5407 
5408 	u8         gids_num[0x10];
5409 	u8         reserved_at_70[0x10];
5410 
5411 	struct mlx5_ifc_array128_auto_bits gid[];
5412 };
5413 
5414 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5415 	u8         opcode[0x10];
5416 	u8         reserved_at_10[0x10];
5417 
5418 	u8         reserved_at_20[0x10];
5419 	u8         op_mod[0x10];
5420 
5421 	u8         other_vport[0x1];
5422 	u8         reserved_at_41[0xb];
5423 	u8         port_num[0x4];
5424 	u8         vport_number[0x10];
5425 
5426 	u8         reserved_at_60[0x10];
5427 	u8         gid_index[0x10];
5428 };
5429 
5430 struct mlx5_ifc_query_hca_vport_context_out_bits {
5431 	u8         status[0x8];
5432 	u8         reserved_at_8[0x18];
5433 
5434 	u8         syndrome[0x20];
5435 
5436 	u8         reserved_at_40[0x40];
5437 
5438 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5439 };
5440 
5441 struct mlx5_ifc_query_hca_vport_context_in_bits {
5442 	u8         opcode[0x10];
5443 	u8         reserved_at_10[0x10];
5444 
5445 	u8         reserved_at_20[0x10];
5446 	u8         op_mod[0x10];
5447 
5448 	u8         other_vport[0x1];
5449 	u8         reserved_at_41[0xb];
5450 	u8         port_num[0x4];
5451 	u8         vport_number[0x10];
5452 
5453 	u8         reserved_at_60[0x20];
5454 };
5455 
5456 struct mlx5_ifc_query_hca_cap_out_bits {
5457 	u8         status[0x8];
5458 	u8         reserved_at_8[0x18];
5459 
5460 	u8         syndrome[0x20];
5461 
5462 	u8         reserved_at_40[0x40];
5463 
5464 	union mlx5_ifc_hca_cap_union_bits capability;
5465 };
5466 
5467 struct mlx5_ifc_query_hca_cap_in_bits {
5468 	u8         opcode[0x10];
5469 	u8         reserved_at_10[0x10];
5470 
5471 	u8         reserved_at_20[0x10];
5472 	u8         op_mod[0x10];
5473 
5474 	u8         other_function[0x1];
5475 	u8         reserved_at_41[0xf];
5476 	u8         function_id[0x10];
5477 
5478 	u8         reserved_at_60[0x20];
5479 };
5480 
5481 struct mlx5_ifc_other_hca_cap_bits {
5482 	u8         roce[0x1];
5483 	u8         reserved_at_1[0x27f];
5484 };
5485 
5486 struct mlx5_ifc_query_other_hca_cap_out_bits {
5487 	u8         status[0x8];
5488 	u8         reserved_at_8[0x18];
5489 
5490 	u8         syndrome[0x20];
5491 
5492 	u8         reserved_at_40[0x40];
5493 
5494 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5495 };
5496 
5497 struct mlx5_ifc_query_other_hca_cap_in_bits {
5498 	u8         opcode[0x10];
5499 	u8         reserved_at_10[0x10];
5500 
5501 	u8         reserved_at_20[0x10];
5502 	u8         op_mod[0x10];
5503 
5504 	u8         reserved_at_40[0x10];
5505 	u8         function_id[0x10];
5506 
5507 	u8         reserved_at_60[0x20];
5508 };
5509 
5510 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5511 	u8         status[0x8];
5512 	u8         reserved_at_8[0x18];
5513 
5514 	u8         syndrome[0x20];
5515 
5516 	u8         reserved_at_40[0x40];
5517 };
5518 
5519 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5520 	u8         opcode[0x10];
5521 	u8         reserved_at_10[0x10];
5522 
5523 	u8         reserved_at_20[0x10];
5524 	u8         op_mod[0x10];
5525 
5526 	u8         reserved_at_40[0x10];
5527 	u8         function_id[0x10];
5528 	u8         field_select[0x20];
5529 
5530 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5531 };
5532 
5533 struct mlx5_ifc_flow_table_context_bits {
5534 	u8         reformat_en[0x1];
5535 	u8         decap_en[0x1];
5536 	u8         sw_owner[0x1];
5537 	u8         termination_table[0x1];
5538 	u8         table_miss_action[0x4];
5539 	u8         level[0x8];
5540 	u8         reserved_at_10[0x8];
5541 	u8         log_size[0x8];
5542 
5543 	u8         reserved_at_20[0x8];
5544 	u8         table_miss_id[0x18];
5545 
5546 	u8         reserved_at_40[0x8];
5547 	u8         lag_master_next_table_id[0x18];
5548 
5549 	u8         reserved_at_60[0x60];
5550 
5551 	u8         sw_owner_icm_root_1[0x40];
5552 
5553 	u8         sw_owner_icm_root_0[0x40];
5554 
5555 };
5556 
5557 struct mlx5_ifc_query_flow_table_out_bits {
5558 	u8         status[0x8];
5559 	u8         reserved_at_8[0x18];
5560 
5561 	u8         syndrome[0x20];
5562 
5563 	u8         reserved_at_40[0x80];
5564 
5565 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5566 };
5567 
5568 struct mlx5_ifc_query_flow_table_in_bits {
5569 	u8         opcode[0x10];
5570 	u8         reserved_at_10[0x10];
5571 
5572 	u8         reserved_at_20[0x10];
5573 	u8         op_mod[0x10];
5574 
5575 	u8         reserved_at_40[0x40];
5576 
5577 	u8         table_type[0x8];
5578 	u8         reserved_at_88[0x18];
5579 
5580 	u8         reserved_at_a0[0x8];
5581 	u8         table_id[0x18];
5582 
5583 	u8         reserved_at_c0[0x140];
5584 };
5585 
5586 struct mlx5_ifc_query_fte_out_bits {
5587 	u8         status[0x8];
5588 	u8         reserved_at_8[0x18];
5589 
5590 	u8         syndrome[0x20];
5591 
5592 	u8         reserved_at_40[0x1c0];
5593 
5594 	struct mlx5_ifc_flow_context_bits flow_context;
5595 };
5596 
5597 struct mlx5_ifc_query_fte_in_bits {
5598 	u8         opcode[0x10];
5599 	u8         reserved_at_10[0x10];
5600 
5601 	u8         reserved_at_20[0x10];
5602 	u8         op_mod[0x10];
5603 
5604 	u8         reserved_at_40[0x40];
5605 
5606 	u8         table_type[0x8];
5607 	u8         reserved_at_88[0x18];
5608 
5609 	u8         reserved_at_a0[0x8];
5610 	u8         table_id[0x18];
5611 
5612 	u8         reserved_at_c0[0x40];
5613 
5614 	u8         flow_index[0x20];
5615 
5616 	u8         reserved_at_120[0xe0];
5617 };
5618 
5619 enum {
5620 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5621 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5622 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5623 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5624 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5625 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
5626 };
5627 
5628 struct mlx5_ifc_query_flow_group_out_bits {
5629 	u8         status[0x8];
5630 	u8         reserved_at_8[0x18];
5631 
5632 	u8         syndrome[0x20];
5633 
5634 	u8         reserved_at_40[0xa0];
5635 
5636 	u8         start_flow_index[0x20];
5637 
5638 	u8         reserved_at_100[0x20];
5639 
5640 	u8         end_flow_index[0x20];
5641 
5642 	u8         reserved_at_140[0xa0];
5643 
5644 	u8         reserved_at_1e0[0x18];
5645 	u8         match_criteria_enable[0x8];
5646 
5647 	struct mlx5_ifc_fte_match_param_bits match_criteria;
5648 
5649 	u8         reserved_at_1200[0xe00];
5650 };
5651 
5652 struct mlx5_ifc_query_flow_group_in_bits {
5653 	u8         opcode[0x10];
5654 	u8         reserved_at_10[0x10];
5655 
5656 	u8         reserved_at_20[0x10];
5657 	u8         op_mod[0x10];
5658 
5659 	u8         reserved_at_40[0x40];
5660 
5661 	u8         table_type[0x8];
5662 	u8         reserved_at_88[0x18];
5663 
5664 	u8         reserved_at_a0[0x8];
5665 	u8         table_id[0x18];
5666 
5667 	u8         group_id[0x20];
5668 
5669 	u8         reserved_at_e0[0x120];
5670 };
5671 
5672 struct mlx5_ifc_query_flow_counter_out_bits {
5673 	u8         status[0x8];
5674 	u8         reserved_at_8[0x18];
5675 
5676 	u8         syndrome[0x20];
5677 
5678 	u8         reserved_at_40[0x40];
5679 
5680 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5681 };
5682 
5683 struct mlx5_ifc_query_flow_counter_in_bits {
5684 	u8         opcode[0x10];
5685 	u8         reserved_at_10[0x10];
5686 
5687 	u8         reserved_at_20[0x10];
5688 	u8         op_mod[0x10];
5689 
5690 	u8         reserved_at_40[0x80];
5691 
5692 	u8         clear[0x1];
5693 	u8         reserved_at_c1[0xf];
5694 	u8         num_of_counters[0x10];
5695 
5696 	u8         flow_counter_id[0x20];
5697 };
5698 
5699 struct mlx5_ifc_query_esw_vport_context_out_bits {
5700 	u8         status[0x8];
5701 	u8         reserved_at_8[0x18];
5702 
5703 	u8         syndrome[0x20];
5704 
5705 	u8         reserved_at_40[0x40];
5706 
5707 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5708 };
5709 
5710 struct mlx5_ifc_query_esw_vport_context_in_bits {
5711 	u8         opcode[0x10];
5712 	u8         reserved_at_10[0x10];
5713 
5714 	u8         reserved_at_20[0x10];
5715 	u8         op_mod[0x10];
5716 
5717 	u8         other_vport[0x1];
5718 	u8         reserved_at_41[0xf];
5719 	u8         vport_number[0x10];
5720 
5721 	u8         reserved_at_60[0x20];
5722 };
5723 
5724 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5725 	u8         status[0x8];
5726 	u8         reserved_at_8[0x18];
5727 
5728 	u8         syndrome[0x20];
5729 
5730 	u8         reserved_at_40[0x40];
5731 };
5732 
5733 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5734 	u8         reserved_at_0[0x1b];
5735 	u8         fdb_to_vport_reg_c_id[0x1];
5736 	u8         vport_cvlan_insert[0x1];
5737 	u8         vport_svlan_insert[0x1];
5738 	u8         vport_cvlan_strip[0x1];
5739 	u8         vport_svlan_strip[0x1];
5740 };
5741 
5742 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5743 	u8         opcode[0x10];
5744 	u8         reserved_at_10[0x10];
5745 
5746 	u8         reserved_at_20[0x10];
5747 	u8         op_mod[0x10];
5748 
5749 	u8         other_vport[0x1];
5750 	u8         reserved_at_41[0xf];
5751 	u8         vport_number[0x10];
5752 
5753 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5754 
5755 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5756 };
5757 
5758 struct mlx5_ifc_query_eq_out_bits {
5759 	u8         status[0x8];
5760 	u8         reserved_at_8[0x18];
5761 
5762 	u8         syndrome[0x20];
5763 
5764 	u8         reserved_at_40[0x40];
5765 
5766 	struct mlx5_ifc_eqc_bits eq_context_entry;
5767 
5768 	u8         reserved_at_280[0x40];
5769 
5770 	u8         event_bitmask[0x40];
5771 
5772 	u8         reserved_at_300[0x580];
5773 
5774 	u8         pas[][0x40];
5775 };
5776 
5777 struct mlx5_ifc_query_eq_in_bits {
5778 	u8         opcode[0x10];
5779 	u8         reserved_at_10[0x10];
5780 
5781 	u8         reserved_at_20[0x10];
5782 	u8         op_mod[0x10];
5783 
5784 	u8         reserved_at_40[0x18];
5785 	u8         eq_number[0x8];
5786 
5787 	u8         reserved_at_60[0x20];
5788 };
5789 
5790 struct mlx5_ifc_packet_reformat_context_in_bits {
5791 	u8         reformat_type[0x8];
5792 	u8         reserved_at_8[0x4];
5793 	u8         reformat_param_0[0x4];
5794 	u8         reserved_at_10[0x6];
5795 	u8         reformat_data_size[0xa];
5796 
5797 	u8         reformat_param_1[0x8];
5798 	u8         reserved_at_28[0x8];
5799 	u8         reformat_data[2][0x8];
5800 
5801 	u8         more_reformat_data[][0x8];
5802 };
5803 
5804 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5805 	u8         status[0x8];
5806 	u8         reserved_at_8[0x18];
5807 
5808 	u8         syndrome[0x20];
5809 
5810 	u8         reserved_at_40[0xa0];
5811 
5812 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5813 };
5814 
5815 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5816 	u8         opcode[0x10];
5817 	u8         reserved_at_10[0x10];
5818 
5819 	u8         reserved_at_20[0x10];
5820 	u8         op_mod[0x10];
5821 
5822 	u8         packet_reformat_id[0x20];
5823 
5824 	u8         reserved_at_60[0xa0];
5825 };
5826 
5827 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5828 	u8         status[0x8];
5829 	u8         reserved_at_8[0x18];
5830 
5831 	u8         syndrome[0x20];
5832 
5833 	u8         packet_reformat_id[0x20];
5834 
5835 	u8         reserved_at_60[0x20];
5836 };
5837 
5838 enum {
5839 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
5840 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
5841 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
5842 };
5843 
5844 enum mlx5_reformat_ctx_type {
5845 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5846 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5847 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5848 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5849 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5850 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
5851 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
5852 };
5853 
5854 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5855 	u8         opcode[0x10];
5856 	u8         reserved_at_10[0x10];
5857 
5858 	u8         reserved_at_20[0x10];
5859 	u8         op_mod[0x10];
5860 
5861 	u8         reserved_at_40[0xa0];
5862 
5863 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5864 };
5865 
5866 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5867 	u8         status[0x8];
5868 	u8         reserved_at_8[0x18];
5869 
5870 	u8         syndrome[0x20];
5871 
5872 	u8         reserved_at_40[0x40];
5873 };
5874 
5875 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5876 	u8         opcode[0x10];
5877 	u8         reserved_at_10[0x10];
5878 
5879 	u8         reserved_20[0x10];
5880 	u8         op_mod[0x10];
5881 
5882 	u8         packet_reformat_id[0x20];
5883 
5884 	u8         reserved_60[0x20];
5885 };
5886 
5887 struct mlx5_ifc_set_action_in_bits {
5888 	u8         action_type[0x4];
5889 	u8         field[0xc];
5890 	u8         reserved_at_10[0x3];
5891 	u8         offset[0x5];
5892 	u8         reserved_at_18[0x3];
5893 	u8         length[0x5];
5894 
5895 	u8         data[0x20];
5896 };
5897 
5898 struct mlx5_ifc_add_action_in_bits {
5899 	u8         action_type[0x4];
5900 	u8         field[0xc];
5901 	u8         reserved_at_10[0x10];
5902 
5903 	u8         data[0x20];
5904 };
5905 
5906 struct mlx5_ifc_copy_action_in_bits {
5907 	u8         action_type[0x4];
5908 	u8         src_field[0xc];
5909 	u8         reserved_at_10[0x3];
5910 	u8         src_offset[0x5];
5911 	u8         reserved_at_18[0x3];
5912 	u8         length[0x5];
5913 
5914 	u8         reserved_at_20[0x4];
5915 	u8         dst_field[0xc];
5916 	u8         reserved_at_30[0x3];
5917 	u8         dst_offset[0x5];
5918 	u8         reserved_at_38[0x8];
5919 };
5920 
5921 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5922 	struct mlx5_ifc_set_action_in_bits  set_action_in;
5923 	struct mlx5_ifc_add_action_in_bits  add_action_in;
5924 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
5925 	u8         reserved_at_0[0x40];
5926 };
5927 
5928 enum {
5929 	MLX5_ACTION_TYPE_SET   = 0x1,
5930 	MLX5_ACTION_TYPE_ADD   = 0x2,
5931 	MLX5_ACTION_TYPE_COPY  = 0x3,
5932 };
5933 
5934 enum {
5935 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5936 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5937 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5938 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5939 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5940 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5941 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5942 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5943 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5944 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5945 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5946 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5947 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5948 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5949 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5950 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5951 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5952 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5953 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5954 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5955 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5956 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5957 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5958 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5959 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5960 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5961 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5962 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5963 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5964 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5965 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5966 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5967 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5968 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5969 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5970 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5971 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
5972 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
5973 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
5974 };
5975 
5976 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5977 	u8         status[0x8];
5978 	u8         reserved_at_8[0x18];
5979 
5980 	u8         syndrome[0x20];
5981 
5982 	u8         modify_header_id[0x20];
5983 
5984 	u8         reserved_at_60[0x20];
5985 };
5986 
5987 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5988 	u8         opcode[0x10];
5989 	u8         reserved_at_10[0x10];
5990 
5991 	u8         reserved_at_20[0x10];
5992 	u8         op_mod[0x10];
5993 
5994 	u8         reserved_at_40[0x20];
5995 
5996 	u8         table_type[0x8];
5997 	u8         reserved_at_68[0x10];
5998 	u8         num_of_actions[0x8];
5999 
6000 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6001 };
6002 
6003 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6004 	u8         status[0x8];
6005 	u8         reserved_at_8[0x18];
6006 
6007 	u8         syndrome[0x20];
6008 
6009 	u8         reserved_at_40[0x40];
6010 };
6011 
6012 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6013 	u8         opcode[0x10];
6014 	u8         reserved_at_10[0x10];
6015 
6016 	u8         reserved_at_20[0x10];
6017 	u8         op_mod[0x10];
6018 
6019 	u8         modify_header_id[0x20];
6020 
6021 	u8         reserved_at_60[0x20];
6022 };
6023 
6024 struct mlx5_ifc_query_modify_header_context_in_bits {
6025 	u8         opcode[0x10];
6026 	u8         uid[0x10];
6027 
6028 	u8         reserved_at_20[0x10];
6029 	u8         op_mod[0x10];
6030 
6031 	u8         modify_header_id[0x20];
6032 
6033 	u8         reserved_at_60[0xa0];
6034 };
6035 
6036 struct mlx5_ifc_query_dct_out_bits {
6037 	u8         status[0x8];
6038 	u8         reserved_at_8[0x18];
6039 
6040 	u8         syndrome[0x20];
6041 
6042 	u8         reserved_at_40[0x40];
6043 
6044 	struct mlx5_ifc_dctc_bits dct_context_entry;
6045 
6046 	u8         reserved_at_280[0x180];
6047 };
6048 
6049 struct mlx5_ifc_query_dct_in_bits {
6050 	u8         opcode[0x10];
6051 	u8         reserved_at_10[0x10];
6052 
6053 	u8         reserved_at_20[0x10];
6054 	u8         op_mod[0x10];
6055 
6056 	u8         reserved_at_40[0x8];
6057 	u8         dctn[0x18];
6058 
6059 	u8         reserved_at_60[0x20];
6060 };
6061 
6062 struct mlx5_ifc_query_cq_out_bits {
6063 	u8         status[0x8];
6064 	u8         reserved_at_8[0x18];
6065 
6066 	u8         syndrome[0x20];
6067 
6068 	u8         reserved_at_40[0x40];
6069 
6070 	struct mlx5_ifc_cqc_bits cq_context;
6071 
6072 	u8         reserved_at_280[0x600];
6073 
6074 	u8         pas[][0x40];
6075 };
6076 
6077 struct mlx5_ifc_query_cq_in_bits {
6078 	u8         opcode[0x10];
6079 	u8         reserved_at_10[0x10];
6080 
6081 	u8         reserved_at_20[0x10];
6082 	u8         op_mod[0x10];
6083 
6084 	u8         reserved_at_40[0x8];
6085 	u8         cqn[0x18];
6086 
6087 	u8         reserved_at_60[0x20];
6088 };
6089 
6090 struct mlx5_ifc_query_cong_status_out_bits {
6091 	u8         status[0x8];
6092 	u8         reserved_at_8[0x18];
6093 
6094 	u8         syndrome[0x20];
6095 
6096 	u8         reserved_at_40[0x20];
6097 
6098 	u8         enable[0x1];
6099 	u8         tag_enable[0x1];
6100 	u8         reserved_at_62[0x1e];
6101 };
6102 
6103 struct mlx5_ifc_query_cong_status_in_bits {
6104 	u8         opcode[0x10];
6105 	u8         reserved_at_10[0x10];
6106 
6107 	u8         reserved_at_20[0x10];
6108 	u8         op_mod[0x10];
6109 
6110 	u8         reserved_at_40[0x18];
6111 	u8         priority[0x4];
6112 	u8         cong_protocol[0x4];
6113 
6114 	u8         reserved_at_60[0x20];
6115 };
6116 
6117 struct mlx5_ifc_query_cong_statistics_out_bits {
6118 	u8         status[0x8];
6119 	u8         reserved_at_8[0x18];
6120 
6121 	u8         syndrome[0x20];
6122 
6123 	u8         reserved_at_40[0x40];
6124 
6125 	u8         rp_cur_flows[0x20];
6126 
6127 	u8         sum_flows[0x20];
6128 
6129 	u8         rp_cnp_ignored_high[0x20];
6130 
6131 	u8         rp_cnp_ignored_low[0x20];
6132 
6133 	u8         rp_cnp_handled_high[0x20];
6134 
6135 	u8         rp_cnp_handled_low[0x20];
6136 
6137 	u8         reserved_at_140[0x100];
6138 
6139 	u8         time_stamp_high[0x20];
6140 
6141 	u8         time_stamp_low[0x20];
6142 
6143 	u8         accumulators_period[0x20];
6144 
6145 	u8         np_ecn_marked_roce_packets_high[0x20];
6146 
6147 	u8         np_ecn_marked_roce_packets_low[0x20];
6148 
6149 	u8         np_cnp_sent_high[0x20];
6150 
6151 	u8         np_cnp_sent_low[0x20];
6152 
6153 	u8         reserved_at_320[0x560];
6154 };
6155 
6156 struct mlx5_ifc_query_cong_statistics_in_bits {
6157 	u8         opcode[0x10];
6158 	u8         reserved_at_10[0x10];
6159 
6160 	u8         reserved_at_20[0x10];
6161 	u8         op_mod[0x10];
6162 
6163 	u8         clear[0x1];
6164 	u8         reserved_at_41[0x1f];
6165 
6166 	u8         reserved_at_60[0x20];
6167 };
6168 
6169 struct mlx5_ifc_query_cong_params_out_bits {
6170 	u8         status[0x8];
6171 	u8         reserved_at_8[0x18];
6172 
6173 	u8         syndrome[0x20];
6174 
6175 	u8         reserved_at_40[0x40];
6176 
6177 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6178 };
6179 
6180 struct mlx5_ifc_query_cong_params_in_bits {
6181 	u8         opcode[0x10];
6182 	u8         reserved_at_10[0x10];
6183 
6184 	u8         reserved_at_20[0x10];
6185 	u8         op_mod[0x10];
6186 
6187 	u8         reserved_at_40[0x1c];
6188 	u8         cong_protocol[0x4];
6189 
6190 	u8         reserved_at_60[0x20];
6191 };
6192 
6193 struct mlx5_ifc_query_adapter_out_bits {
6194 	u8         status[0x8];
6195 	u8         reserved_at_8[0x18];
6196 
6197 	u8         syndrome[0x20];
6198 
6199 	u8         reserved_at_40[0x40];
6200 
6201 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6202 };
6203 
6204 struct mlx5_ifc_query_adapter_in_bits {
6205 	u8         opcode[0x10];
6206 	u8         reserved_at_10[0x10];
6207 
6208 	u8         reserved_at_20[0x10];
6209 	u8         op_mod[0x10];
6210 
6211 	u8         reserved_at_40[0x40];
6212 };
6213 
6214 struct mlx5_ifc_qp_2rst_out_bits {
6215 	u8         status[0x8];
6216 	u8         reserved_at_8[0x18];
6217 
6218 	u8         syndrome[0x20];
6219 
6220 	u8         reserved_at_40[0x40];
6221 };
6222 
6223 struct mlx5_ifc_qp_2rst_in_bits {
6224 	u8         opcode[0x10];
6225 	u8         uid[0x10];
6226 
6227 	u8         reserved_at_20[0x10];
6228 	u8         op_mod[0x10];
6229 
6230 	u8         reserved_at_40[0x8];
6231 	u8         qpn[0x18];
6232 
6233 	u8         reserved_at_60[0x20];
6234 };
6235 
6236 struct mlx5_ifc_qp_2err_out_bits {
6237 	u8         status[0x8];
6238 	u8         reserved_at_8[0x18];
6239 
6240 	u8         syndrome[0x20];
6241 
6242 	u8         reserved_at_40[0x40];
6243 };
6244 
6245 struct mlx5_ifc_qp_2err_in_bits {
6246 	u8         opcode[0x10];
6247 	u8         uid[0x10];
6248 
6249 	u8         reserved_at_20[0x10];
6250 	u8         op_mod[0x10];
6251 
6252 	u8         reserved_at_40[0x8];
6253 	u8         qpn[0x18];
6254 
6255 	u8         reserved_at_60[0x20];
6256 };
6257 
6258 struct mlx5_ifc_page_fault_resume_out_bits {
6259 	u8         status[0x8];
6260 	u8         reserved_at_8[0x18];
6261 
6262 	u8         syndrome[0x20];
6263 
6264 	u8         reserved_at_40[0x40];
6265 };
6266 
6267 struct mlx5_ifc_page_fault_resume_in_bits {
6268 	u8         opcode[0x10];
6269 	u8         reserved_at_10[0x10];
6270 
6271 	u8         reserved_at_20[0x10];
6272 	u8         op_mod[0x10];
6273 
6274 	u8         error[0x1];
6275 	u8         reserved_at_41[0x4];
6276 	u8         page_fault_type[0x3];
6277 	u8         wq_number[0x18];
6278 
6279 	u8         reserved_at_60[0x8];
6280 	u8         token[0x18];
6281 };
6282 
6283 struct mlx5_ifc_nop_out_bits {
6284 	u8         status[0x8];
6285 	u8         reserved_at_8[0x18];
6286 
6287 	u8         syndrome[0x20];
6288 
6289 	u8         reserved_at_40[0x40];
6290 };
6291 
6292 struct mlx5_ifc_nop_in_bits {
6293 	u8         opcode[0x10];
6294 	u8         reserved_at_10[0x10];
6295 
6296 	u8         reserved_at_20[0x10];
6297 	u8         op_mod[0x10];
6298 
6299 	u8         reserved_at_40[0x40];
6300 };
6301 
6302 struct mlx5_ifc_modify_vport_state_out_bits {
6303 	u8         status[0x8];
6304 	u8         reserved_at_8[0x18];
6305 
6306 	u8         syndrome[0x20];
6307 
6308 	u8         reserved_at_40[0x40];
6309 };
6310 
6311 struct mlx5_ifc_modify_vport_state_in_bits {
6312 	u8         opcode[0x10];
6313 	u8         reserved_at_10[0x10];
6314 
6315 	u8         reserved_at_20[0x10];
6316 	u8         op_mod[0x10];
6317 
6318 	u8         other_vport[0x1];
6319 	u8         reserved_at_41[0xf];
6320 	u8         vport_number[0x10];
6321 
6322 	u8         reserved_at_60[0x18];
6323 	u8         admin_state[0x4];
6324 	u8         reserved_at_7c[0x4];
6325 };
6326 
6327 struct mlx5_ifc_modify_tis_out_bits {
6328 	u8         status[0x8];
6329 	u8         reserved_at_8[0x18];
6330 
6331 	u8         syndrome[0x20];
6332 
6333 	u8         reserved_at_40[0x40];
6334 };
6335 
6336 struct mlx5_ifc_modify_tis_bitmask_bits {
6337 	u8         reserved_at_0[0x20];
6338 
6339 	u8         reserved_at_20[0x1d];
6340 	u8         lag_tx_port_affinity[0x1];
6341 	u8         strict_lag_tx_port_affinity[0x1];
6342 	u8         prio[0x1];
6343 };
6344 
6345 struct mlx5_ifc_modify_tis_in_bits {
6346 	u8         opcode[0x10];
6347 	u8         uid[0x10];
6348 
6349 	u8         reserved_at_20[0x10];
6350 	u8         op_mod[0x10];
6351 
6352 	u8         reserved_at_40[0x8];
6353 	u8         tisn[0x18];
6354 
6355 	u8         reserved_at_60[0x20];
6356 
6357 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6358 
6359 	u8         reserved_at_c0[0x40];
6360 
6361 	struct mlx5_ifc_tisc_bits ctx;
6362 };
6363 
6364 struct mlx5_ifc_modify_tir_bitmask_bits {
6365 	u8	   reserved_at_0[0x20];
6366 
6367 	u8         reserved_at_20[0x1b];
6368 	u8         self_lb_en[0x1];
6369 	u8         reserved_at_3c[0x1];
6370 	u8         hash[0x1];
6371 	u8         reserved_at_3e[0x1];
6372 	u8         lro[0x1];
6373 };
6374 
6375 struct mlx5_ifc_modify_tir_out_bits {
6376 	u8         status[0x8];
6377 	u8         reserved_at_8[0x18];
6378 
6379 	u8         syndrome[0x20];
6380 
6381 	u8         reserved_at_40[0x40];
6382 };
6383 
6384 struct mlx5_ifc_modify_tir_in_bits {
6385 	u8         opcode[0x10];
6386 	u8         uid[0x10];
6387 
6388 	u8         reserved_at_20[0x10];
6389 	u8         op_mod[0x10];
6390 
6391 	u8         reserved_at_40[0x8];
6392 	u8         tirn[0x18];
6393 
6394 	u8         reserved_at_60[0x20];
6395 
6396 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6397 
6398 	u8         reserved_at_c0[0x40];
6399 
6400 	struct mlx5_ifc_tirc_bits ctx;
6401 };
6402 
6403 struct mlx5_ifc_modify_sq_out_bits {
6404 	u8         status[0x8];
6405 	u8         reserved_at_8[0x18];
6406 
6407 	u8         syndrome[0x20];
6408 
6409 	u8         reserved_at_40[0x40];
6410 };
6411 
6412 struct mlx5_ifc_modify_sq_in_bits {
6413 	u8         opcode[0x10];
6414 	u8         uid[0x10];
6415 
6416 	u8         reserved_at_20[0x10];
6417 	u8         op_mod[0x10];
6418 
6419 	u8         sq_state[0x4];
6420 	u8         reserved_at_44[0x4];
6421 	u8         sqn[0x18];
6422 
6423 	u8         reserved_at_60[0x20];
6424 
6425 	u8         modify_bitmask[0x40];
6426 
6427 	u8         reserved_at_c0[0x40];
6428 
6429 	struct mlx5_ifc_sqc_bits ctx;
6430 };
6431 
6432 struct mlx5_ifc_modify_scheduling_element_out_bits {
6433 	u8         status[0x8];
6434 	u8         reserved_at_8[0x18];
6435 
6436 	u8         syndrome[0x20];
6437 
6438 	u8         reserved_at_40[0x1c0];
6439 };
6440 
6441 enum {
6442 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6443 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6444 };
6445 
6446 struct mlx5_ifc_modify_scheduling_element_in_bits {
6447 	u8         opcode[0x10];
6448 	u8         reserved_at_10[0x10];
6449 
6450 	u8         reserved_at_20[0x10];
6451 	u8         op_mod[0x10];
6452 
6453 	u8         scheduling_hierarchy[0x8];
6454 	u8         reserved_at_48[0x18];
6455 
6456 	u8         scheduling_element_id[0x20];
6457 
6458 	u8         reserved_at_80[0x20];
6459 
6460 	u8         modify_bitmask[0x20];
6461 
6462 	u8         reserved_at_c0[0x40];
6463 
6464 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
6465 
6466 	u8         reserved_at_300[0x100];
6467 };
6468 
6469 struct mlx5_ifc_modify_rqt_out_bits {
6470 	u8         status[0x8];
6471 	u8         reserved_at_8[0x18];
6472 
6473 	u8         syndrome[0x20];
6474 
6475 	u8         reserved_at_40[0x40];
6476 };
6477 
6478 struct mlx5_ifc_rqt_bitmask_bits {
6479 	u8	   reserved_at_0[0x20];
6480 
6481 	u8         reserved_at_20[0x1f];
6482 	u8         rqn_list[0x1];
6483 };
6484 
6485 struct mlx5_ifc_modify_rqt_in_bits {
6486 	u8         opcode[0x10];
6487 	u8         uid[0x10];
6488 
6489 	u8         reserved_at_20[0x10];
6490 	u8         op_mod[0x10];
6491 
6492 	u8         reserved_at_40[0x8];
6493 	u8         rqtn[0x18];
6494 
6495 	u8         reserved_at_60[0x20];
6496 
6497 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
6498 
6499 	u8         reserved_at_c0[0x40];
6500 
6501 	struct mlx5_ifc_rqtc_bits ctx;
6502 };
6503 
6504 struct mlx5_ifc_modify_rq_out_bits {
6505 	u8         status[0x8];
6506 	u8         reserved_at_8[0x18];
6507 
6508 	u8         syndrome[0x20];
6509 
6510 	u8         reserved_at_40[0x40];
6511 };
6512 
6513 enum {
6514 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6515 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6516 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6517 };
6518 
6519 struct mlx5_ifc_modify_rq_in_bits {
6520 	u8         opcode[0x10];
6521 	u8         uid[0x10];
6522 
6523 	u8         reserved_at_20[0x10];
6524 	u8         op_mod[0x10];
6525 
6526 	u8         rq_state[0x4];
6527 	u8         reserved_at_44[0x4];
6528 	u8         rqn[0x18];
6529 
6530 	u8         reserved_at_60[0x20];
6531 
6532 	u8         modify_bitmask[0x40];
6533 
6534 	u8         reserved_at_c0[0x40];
6535 
6536 	struct mlx5_ifc_rqc_bits ctx;
6537 };
6538 
6539 struct mlx5_ifc_modify_rmp_out_bits {
6540 	u8         status[0x8];
6541 	u8         reserved_at_8[0x18];
6542 
6543 	u8         syndrome[0x20];
6544 
6545 	u8         reserved_at_40[0x40];
6546 };
6547 
6548 struct mlx5_ifc_rmp_bitmask_bits {
6549 	u8	   reserved_at_0[0x20];
6550 
6551 	u8         reserved_at_20[0x1f];
6552 	u8         lwm[0x1];
6553 };
6554 
6555 struct mlx5_ifc_modify_rmp_in_bits {
6556 	u8         opcode[0x10];
6557 	u8         uid[0x10];
6558 
6559 	u8         reserved_at_20[0x10];
6560 	u8         op_mod[0x10];
6561 
6562 	u8         rmp_state[0x4];
6563 	u8         reserved_at_44[0x4];
6564 	u8         rmpn[0x18];
6565 
6566 	u8         reserved_at_60[0x20];
6567 
6568 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
6569 
6570 	u8         reserved_at_c0[0x40];
6571 
6572 	struct mlx5_ifc_rmpc_bits ctx;
6573 };
6574 
6575 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6576 	u8         status[0x8];
6577 	u8         reserved_at_8[0x18];
6578 
6579 	u8         syndrome[0x20];
6580 
6581 	u8         reserved_at_40[0x40];
6582 };
6583 
6584 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6585 	u8         reserved_at_0[0x12];
6586 	u8	   affiliation[0x1];
6587 	u8	   reserved_at_13[0x1];
6588 	u8         disable_uc_local_lb[0x1];
6589 	u8         disable_mc_local_lb[0x1];
6590 	u8         node_guid[0x1];
6591 	u8         port_guid[0x1];
6592 	u8         min_inline[0x1];
6593 	u8         mtu[0x1];
6594 	u8         change_event[0x1];
6595 	u8         promisc[0x1];
6596 	u8         permanent_address[0x1];
6597 	u8         addresses_list[0x1];
6598 	u8         roce_en[0x1];
6599 	u8         reserved_at_1f[0x1];
6600 };
6601 
6602 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6603 	u8         opcode[0x10];
6604 	u8         reserved_at_10[0x10];
6605 
6606 	u8         reserved_at_20[0x10];
6607 	u8         op_mod[0x10];
6608 
6609 	u8         other_vport[0x1];
6610 	u8         reserved_at_41[0xf];
6611 	u8         vport_number[0x10];
6612 
6613 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6614 
6615 	u8         reserved_at_80[0x780];
6616 
6617 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6618 };
6619 
6620 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6621 	u8         status[0x8];
6622 	u8         reserved_at_8[0x18];
6623 
6624 	u8         syndrome[0x20];
6625 
6626 	u8         reserved_at_40[0x40];
6627 };
6628 
6629 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6630 	u8         opcode[0x10];
6631 	u8         reserved_at_10[0x10];
6632 
6633 	u8         reserved_at_20[0x10];
6634 	u8         op_mod[0x10];
6635 
6636 	u8         other_vport[0x1];
6637 	u8         reserved_at_41[0xb];
6638 	u8         port_num[0x4];
6639 	u8         vport_number[0x10];
6640 
6641 	u8         reserved_at_60[0x20];
6642 
6643 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6644 };
6645 
6646 struct mlx5_ifc_modify_cq_out_bits {
6647 	u8         status[0x8];
6648 	u8         reserved_at_8[0x18];
6649 
6650 	u8         syndrome[0x20];
6651 
6652 	u8         reserved_at_40[0x40];
6653 };
6654 
6655 enum {
6656 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6657 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6658 };
6659 
6660 struct mlx5_ifc_modify_cq_in_bits {
6661 	u8         opcode[0x10];
6662 	u8         uid[0x10];
6663 
6664 	u8         reserved_at_20[0x10];
6665 	u8         op_mod[0x10];
6666 
6667 	u8         reserved_at_40[0x8];
6668 	u8         cqn[0x18];
6669 
6670 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6671 
6672 	struct mlx5_ifc_cqc_bits cq_context;
6673 
6674 	u8         reserved_at_280[0x60];
6675 
6676 	u8         cq_umem_valid[0x1];
6677 	u8         reserved_at_2e1[0x1f];
6678 
6679 	u8         reserved_at_300[0x580];
6680 
6681 	u8         pas[][0x40];
6682 };
6683 
6684 struct mlx5_ifc_modify_cong_status_out_bits {
6685 	u8         status[0x8];
6686 	u8         reserved_at_8[0x18];
6687 
6688 	u8         syndrome[0x20];
6689 
6690 	u8         reserved_at_40[0x40];
6691 };
6692 
6693 struct mlx5_ifc_modify_cong_status_in_bits {
6694 	u8         opcode[0x10];
6695 	u8         reserved_at_10[0x10];
6696 
6697 	u8         reserved_at_20[0x10];
6698 	u8         op_mod[0x10];
6699 
6700 	u8         reserved_at_40[0x18];
6701 	u8         priority[0x4];
6702 	u8         cong_protocol[0x4];
6703 
6704 	u8         enable[0x1];
6705 	u8         tag_enable[0x1];
6706 	u8         reserved_at_62[0x1e];
6707 };
6708 
6709 struct mlx5_ifc_modify_cong_params_out_bits {
6710 	u8         status[0x8];
6711 	u8         reserved_at_8[0x18];
6712 
6713 	u8         syndrome[0x20];
6714 
6715 	u8         reserved_at_40[0x40];
6716 };
6717 
6718 struct mlx5_ifc_modify_cong_params_in_bits {
6719 	u8         opcode[0x10];
6720 	u8         reserved_at_10[0x10];
6721 
6722 	u8         reserved_at_20[0x10];
6723 	u8         op_mod[0x10];
6724 
6725 	u8         reserved_at_40[0x1c];
6726 	u8         cong_protocol[0x4];
6727 
6728 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6729 
6730 	u8         reserved_at_80[0x80];
6731 
6732 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6733 };
6734 
6735 struct mlx5_ifc_manage_pages_out_bits {
6736 	u8         status[0x8];
6737 	u8         reserved_at_8[0x18];
6738 
6739 	u8         syndrome[0x20];
6740 
6741 	u8         output_num_entries[0x20];
6742 
6743 	u8         reserved_at_60[0x20];
6744 
6745 	u8         pas[][0x40];
6746 };
6747 
6748 enum {
6749 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6750 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6751 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6752 };
6753 
6754 struct mlx5_ifc_manage_pages_in_bits {
6755 	u8         opcode[0x10];
6756 	u8         reserved_at_10[0x10];
6757 
6758 	u8         reserved_at_20[0x10];
6759 	u8         op_mod[0x10];
6760 
6761 	u8         embedded_cpu_function[0x1];
6762 	u8         reserved_at_41[0xf];
6763 	u8         function_id[0x10];
6764 
6765 	u8         input_num_entries[0x20];
6766 
6767 	u8         pas[][0x40];
6768 };
6769 
6770 struct mlx5_ifc_mad_ifc_out_bits {
6771 	u8         status[0x8];
6772 	u8         reserved_at_8[0x18];
6773 
6774 	u8         syndrome[0x20];
6775 
6776 	u8         reserved_at_40[0x40];
6777 
6778 	u8         response_mad_packet[256][0x8];
6779 };
6780 
6781 struct mlx5_ifc_mad_ifc_in_bits {
6782 	u8         opcode[0x10];
6783 	u8         reserved_at_10[0x10];
6784 
6785 	u8         reserved_at_20[0x10];
6786 	u8         op_mod[0x10];
6787 
6788 	u8         remote_lid[0x10];
6789 	u8         reserved_at_50[0x8];
6790 	u8         port[0x8];
6791 
6792 	u8         reserved_at_60[0x20];
6793 
6794 	u8         mad[256][0x8];
6795 };
6796 
6797 struct mlx5_ifc_init_hca_out_bits {
6798 	u8         status[0x8];
6799 	u8         reserved_at_8[0x18];
6800 
6801 	u8         syndrome[0x20];
6802 
6803 	u8         reserved_at_40[0x40];
6804 };
6805 
6806 struct mlx5_ifc_init_hca_in_bits {
6807 	u8         opcode[0x10];
6808 	u8         reserved_at_10[0x10];
6809 
6810 	u8         reserved_at_20[0x10];
6811 	u8         op_mod[0x10];
6812 
6813 	u8         reserved_at_40[0x40];
6814 	u8	   sw_owner_id[4][0x20];
6815 };
6816 
6817 struct mlx5_ifc_init2rtr_qp_out_bits {
6818 	u8         status[0x8];
6819 	u8         reserved_at_8[0x18];
6820 
6821 	u8         syndrome[0x20];
6822 
6823 	u8         reserved_at_40[0x20];
6824 	u8         ece[0x20];
6825 };
6826 
6827 struct mlx5_ifc_init2rtr_qp_in_bits {
6828 	u8         opcode[0x10];
6829 	u8         uid[0x10];
6830 
6831 	u8         reserved_at_20[0x10];
6832 	u8         op_mod[0x10];
6833 
6834 	u8         reserved_at_40[0x8];
6835 	u8         qpn[0x18];
6836 
6837 	u8         reserved_at_60[0x20];
6838 
6839 	u8         opt_param_mask[0x20];
6840 
6841 	u8         ece[0x20];
6842 
6843 	struct mlx5_ifc_qpc_bits qpc;
6844 
6845 	u8         reserved_at_800[0x80];
6846 };
6847 
6848 struct mlx5_ifc_init2init_qp_out_bits {
6849 	u8         status[0x8];
6850 	u8         reserved_at_8[0x18];
6851 
6852 	u8         syndrome[0x20];
6853 
6854 	u8         reserved_at_40[0x20];
6855 	u8         ece[0x20];
6856 };
6857 
6858 struct mlx5_ifc_init2init_qp_in_bits {
6859 	u8         opcode[0x10];
6860 	u8         uid[0x10];
6861 
6862 	u8         reserved_at_20[0x10];
6863 	u8         op_mod[0x10];
6864 
6865 	u8         reserved_at_40[0x8];
6866 	u8         qpn[0x18];
6867 
6868 	u8         reserved_at_60[0x20];
6869 
6870 	u8         opt_param_mask[0x20];
6871 
6872 	u8         ece[0x20];
6873 
6874 	struct mlx5_ifc_qpc_bits qpc;
6875 
6876 	u8         reserved_at_800[0x80];
6877 };
6878 
6879 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6880 	u8         status[0x8];
6881 	u8         reserved_at_8[0x18];
6882 
6883 	u8         syndrome[0x20];
6884 
6885 	u8         reserved_at_40[0x40];
6886 
6887 	u8         packet_headers_log[128][0x8];
6888 
6889 	u8         packet_syndrome[64][0x8];
6890 };
6891 
6892 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6893 	u8         opcode[0x10];
6894 	u8         reserved_at_10[0x10];
6895 
6896 	u8         reserved_at_20[0x10];
6897 	u8         op_mod[0x10];
6898 
6899 	u8         reserved_at_40[0x40];
6900 };
6901 
6902 struct mlx5_ifc_gen_eqe_in_bits {
6903 	u8         opcode[0x10];
6904 	u8         reserved_at_10[0x10];
6905 
6906 	u8         reserved_at_20[0x10];
6907 	u8         op_mod[0x10];
6908 
6909 	u8         reserved_at_40[0x18];
6910 	u8         eq_number[0x8];
6911 
6912 	u8         reserved_at_60[0x20];
6913 
6914 	u8         eqe[64][0x8];
6915 };
6916 
6917 struct mlx5_ifc_gen_eq_out_bits {
6918 	u8         status[0x8];
6919 	u8         reserved_at_8[0x18];
6920 
6921 	u8         syndrome[0x20];
6922 
6923 	u8         reserved_at_40[0x40];
6924 };
6925 
6926 struct mlx5_ifc_enable_hca_out_bits {
6927 	u8         status[0x8];
6928 	u8         reserved_at_8[0x18];
6929 
6930 	u8         syndrome[0x20];
6931 
6932 	u8         reserved_at_40[0x20];
6933 };
6934 
6935 struct mlx5_ifc_enable_hca_in_bits {
6936 	u8         opcode[0x10];
6937 	u8         reserved_at_10[0x10];
6938 
6939 	u8         reserved_at_20[0x10];
6940 	u8         op_mod[0x10];
6941 
6942 	u8         embedded_cpu_function[0x1];
6943 	u8         reserved_at_41[0xf];
6944 	u8         function_id[0x10];
6945 
6946 	u8         reserved_at_60[0x20];
6947 };
6948 
6949 struct mlx5_ifc_drain_dct_out_bits {
6950 	u8         status[0x8];
6951 	u8         reserved_at_8[0x18];
6952 
6953 	u8         syndrome[0x20];
6954 
6955 	u8         reserved_at_40[0x40];
6956 };
6957 
6958 struct mlx5_ifc_drain_dct_in_bits {
6959 	u8         opcode[0x10];
6960 	u8         uid[0x10];
6961 
6962 	u8         reserved_at_20[0x10];
6963 	u8         op_mod[0x10];
6964 
6965 	u8         reserved_at_40[0x8];
6966 	u8         dctn[0x18];
6967 
6968 	u8         reserved_at_60[0x20];
6969 };
6970 
6971 struct mlx5_ifc_disable_hca_out_bits {
6972 	u8         status[0x8];
6973 	u8         reserved_at_8[0x18];
6974 
6975 	u8         syndrome[0x20];
6976 
6977 	u8         reserved_at_40[0x20];
6978 };
6979 
6980 struct mlx5_ifc_disable_hca_in_bits {
6981 	u8         opcode[0x10];
6982 	u8         reserved_at_10[0x10];
6983 
6984 	u8         reserved_at_20[0x10];
6985 	u8         op_mod[0x10];
6986 
6987 	u8         embedded_cpu_function[0x1];
6988 	u8         reserved_at_41[0xf];
6989 	u8         function_id[0x10];
6990 
6991 	u8         reserved_at_60[0x20];
6992 };
6993 
6994 struct mlx5_ifc_detach_from_mcg_out_bits {
6995 	u8         status[0x8];
6996 	u8         reserved_at_8[0x18];
6997 
6998 	u8         syndrome[0x20];
6999 
7000 	u8         reserved_at_40[0x40];
7001 };
7002 
7003 struct mlx5_ifc_detach_from_mcg_in_bits {
7004 	u8         opcode[0x10];
7005 	u8         uid[0x10];
7006 
7007 	u8         reserved_at_20[0x10];
7008 	u8         op_mod[0x10];
7009 
7010 	u8         reserved_at_40[0x8];
7011 	u8         qpn[0x18];
7012 
7013 	u8         reserved_at_60[0x20];
7014 
7015 	u8         multicast_gid[16][0x8];
7016 };
7017 
7018 struct mlx5_ifc_destroy_xrq_out_bits {
7019 	u8         status[0x8];
7020 	u8         reserved_at_8[0x18];
7021 
7022 	u8         syndrome[0x20];
7023 
7024 	u8         reserved_at_40[0x40];
7025 };
7026 
7027 struct mlx5_ifc_destroy_xrq_in_bits {
7028 	u8         opcode[0x10];
7029 	u8         uid[0x10];
7030 
7031 	u8         reserved_at_20[0x10];
7032 	u8         op_mod[0x10];
7033 
7034 	u8         reserved_at_40[0x8];
7035 	u8         xrqn[0x18];
7036 
7037 	u8         reserved_at_60[0x20];
7038 };
7039 
7040 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7041 	u8         status[0x8];
7042 	u8         reserved_at_8[0x18];
7043 
7044 	u8         syndrome[0x20];
7045 
7046 	u8         reserved_at_40[0x40];
7047 };
7048 
7049 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7050 	u8         opcode[0x10];
7051 	u8         uid[0x10];
7052 
7053 	u8         reserved_at_20[0x10];
7054 	u8         op_mod[0x10];
7055 
7056 	u8         reserved_at_40[0x8];
7057 	u8         xrc_srqn[0x18];
7058 
7059 	u8         reserved_at_60[0x20];
7060 };
7061 
7062 struct mlx5_ifc_destroy_tis_out_bits {
7063 	u8         status[0x8];
7064 	u8         reserved_at_8[0x18];
7065 
7066 	u8         syndrome[0x20];
7067 
7068 	u8         reserved_at_40[0x40];
7069 };
7070 
7071 struct mlx5_ifc_destroy_tis_in_bits {
7072 	u8         opcode[0x10];
7073 	u8         uid[0x10];
7074 
7075 	u8         reserved_at_20[0x10];
7076 	u8         op_mod[0x10];
7077 
7078 	u8         reserved_at_40[0x8];
7079 	u8         tisn[0x18];
7080 
7081 	u8         reserved_at_60[0x20];
7082 };
7083 
7084 struct mlx5_ifc_destroy_tir_out_bits {
7085 	u8         status[0x8];
7086 	u8         reserved_at_8[0x18];
7087 
7088 	u8         syndrome[0x20];
7089 
7090 	u8         reserved_at_40[0x40];
7091 };
7092 
7093 struct mlx5_ifc_destroy_tir_in_bits {
7094 	u8         opcode[0x10];
7095 	u8         uid[0x10];
7096 
7097 	u8         reserved_at_20[0x10];
7098 	u8         op_mod[0x10];
7099 
7100 	u8         reserved_at_40[0x8];
7101 	u8         tirn[0x18];
7102 
7103 	u8         reserved_at_60[0x20];
7104 };
7105 
7106 struct mlx5_ifc_destroy_srq_out_bits {
7107 	u8         status[0x8];
7108 	u8         reserved_at_8[0x18];
7109 
7110 	u8         syndrome[0x20];
7111 
7112 	u8         reserved_at_40[0x40];
7113 };
7114 
7115 struct mlx5_ifc_destroy_srq_in_bits {
7116 	u8         opcode[0x10];
7117 	u8         uid[0x10];
7118 
7119 	u8         reserved_at_20[0x10];
7120 	u8         op_mod[0x10];
7121 
7122 	u8         reserved_at_40[0x8];
7123 	u8         srqn[0x18];
7124 
7125 	u8         reserved_at_60[0x20];
7126 };
7127 
7128 struct mlx5_ifc_destroy_sq_out_bits {
7129 	u8         status[0x8];
7130 	u8         reserved_at_8[0x18];
7131 
7132 	u8         syndrome[0x20];
7133 
7134 	u8         reserved_at_40[0x40];
7135 };
7136 
7137 struct mlx5_ifc_destroy_sq_in_bits {
7138 	u8         opcode[0x10];
7139 	u8         uid[0x10];
7140 
7141 	u8         reserved_at_20[0x10];
7142 	u8         op_mod[0x10];
7143 
7144 	u8         reserved_at_40[0x8];
7145 	u8         sqn[0x18];
7146 
7147 	u8         reserved_at_60[0x20];
7148 };
7149 
7150 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7151 	u8         status[0x8];
7152 	u8         reserved_at_8[0x18];
7153 
7154 	u8         syndrome[0x20];
7155 
7156 	u8         reserved_at_40[0x1c0];
7157 };
7158 
7159 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7160 	u8         opcode[0x10];
7161 	u8         reserved_at_10[0x10];
7162 
7163 	u8         reserved_at_20[0x10];
7164 	u8         op_mod[0x10];
7165 
7166 	u8         scheduling_hierarchy[0x8];
7167 	u8         reserved_at_48[0x18];
7168 
7169 	u8         scheduling_element_id[0x20];
7170 
7171 	u8         reserved_at_80[0x180];
7172 };
7173 
7174 struct mlx5_ifc_destroy_rqt_out_bits {
7175 	u8         status[0x8];
7176 	u8         reserved_at_8[0x18];
7177 
7178 	u8         syndrome[0x20];
7179 
7180 	u8         reserved_at_40[0x40];
7181 };
7182 
7183 struct mlx5_ifc_destroy_rqt_in_bits {
7184 	u8         opcode[0x10];
7185 	u8         uid[0x10];
7186 
7187 	u8         reserved_at_20[0x10];
7188 	u8         op_mod[0x10];
7189 
7190 	u8         reserved_at_40[0x8];
7191 	u8         rqtn[0x18];
7192 
7193 	u8         reserved_at_60[0x20];
7194 };
7195 
7196 struct mlx5_ifc_destroy_rq_out_bits {
7197 	u8         status[0x8];
7198 	u8         reserved_at_8[0x18];
7199 
7200 	u8         syndrome[0x20];
7201 
7202 	u8         reserved_at_40[0x40];
7203 };
7204 
7205 struct mlx5_ifc_destroy_rq_in_bits {
7206 	u8         opcode[0x10];
7207 	u8         uid[0x10];
7208 
7209 	u8         reserved_at_20[0x10];
7210 	u8         op_mod[0x10];
7211 
7212 	u8         reserved_at_40[0x8];
7213 	u8         rqn[0x18];
7214 
7215 	u8         reserved_at_60[0x20];
7216 };
7217 
7218 struct mlx5_ifc_set_delay_drop_params_in_bits {
7219 	u8         opcode[0x10];
7220 	u8         reserved_at_10[0x10];
7221 
7222 	u8         reserved_at_20[0x10];
7223 	u8         op_mod[0x10];
7224 
7225 	u8         reserved_at_40[0x20];
7226 
7227 	u8         reserved_at_60[0x10];
7228 	u8         delay_drop_timeout[0x10];
7229 };
7230 
7231 struct mlx5_ifc_set_delay_drop_params_out_bits {
7232 	u8         status[0x8];
7233 	u8         reserved_at_8[0x18];
7234 
7235 	u8         syndrome[0x20];
7236 
7237 	u8         reserved_at_40[0x40];
7238 };
7239 
7240 struct mlx5_ifc_destroy_rmp_out_bits {
7241 	u8         status[0x8];
7242 	u8         reserved_at_8[0x18];
7243 
7244 	u8         syndrome[0x20];
7245 
7246 	u8         reserved_at_40[0x40];
7247 };
7248 
7249 struct mlx5_ifc_destroy_rmp_in_bits {
7250 	u8         opcode[0x10];
7251 	u8         uid[0x10];
7252 
7253 	u8         reserved_at_20[0x10];
7254 	u8         op_mod[0x10];
7255 
7256 	u8         reserved_at_40[0x8];
7257 	u8         rmpn[0x18];
7258 
7259 	u8         reserved_at_60[0x20];
7260 };
7261 
7262 struct mlx5_ifc_destroy_qp_out_bits {
7263 	u8         status[0x8];
7264 	u8         reserved_at_8[0x18];
7265 
7266 	u8         syndrome[0x20];
7267 
7268 	u8         reserved_at_40[0x40];
7269 };
7270 
7271 struct mlx5_ifc_destroy_qp_in_bits {
7272 	u8         opcode[0x10];
7273 	u8         uid[0x10];
7274 
7275 	u8         reserved_at_20[0x10];
7276 	u8         op_mod[0x10];
7277 
7278 	u8         reserved_at_40[0x8];
7279 	u8         qpn[0x18];
7280 
7281 	u8         reserved_at_60[0x20];
7282 };
7283 
7284 struct mlx5_ifc_destroy_psv_out_bits {
7285 	u8         status[0x8];
7286 	u8         reserved_at_8[0x18];
7287 
7288 	u8         syndrome[0x20];
7289 
7290 	u8         reserved_at_40[0x40];
7291 };
7292 
7293 struct mlx5_ifc_destroy_psv_in_bits {
7294 	u8         opcode[0x10];
7295 	u8         reserved_at_10[0x10];
7296 
7297 	u8         reserved_at_20[0x10];
7298 	u8         op_mod[0x10];
7299 
7300 	u8         reserved_at_40[0x8];
7301 	u8         psvn[0x18];
7302 
7303 	u8         reserved_at_60[0x20];
7304 };
7305 
7306 struct mlx5_ifc_destroy_mkey_out_bits {
7307 	u8         status[0x8];
7308 	u8         reserved_at_8[0x18];
7309 
7310 	u8         syndrome[0x20];
7311 
7312 	u8         reserved_at_40[0x40];
7313 };
7314 
7315 struct mlx5_ifc_destroy_mkey_in_bits {
7316 	u8         opcode[0x10];
7317 	u8         uid[0x10];
7318 
7319 	u8         reserved_at_20[0x10];
7320 	u8         op_mod[0x10];
7321 
7322 	u8         reserved_at_40[0x8];
7323 	u8         mkey_index[0x18];
7324 
7325 	u8         reserved_at_60[0x20];
7326 };
7327 
7328 struct mlx5_ifc_destroy_flow_table_out_bits {
7329 	u8         status[0x8];
7330 	u8         reserved_at_8[0x18];
7331 
7332 	u8         syndrome[0x20];
7333 
7334 	u8         reserved_at_40[0x40];
7335 };
7336 
7337 struct mlx5_ifc_destroy_flow_table_in_bits {
7338 	u8         opcode[0x10];
7339 	u8         reserved_at_10[0x10];
7340 
7341 	u8         reserved_at_20[0x10];
7342 	u8         op_mod[0x10];
7343 
7344 	u8         other_vport[0x1];
7345 	u8         reserved_at_41[0xf];
7346 	u8         vport_number[0x10];
7347 
7348 	u8         reserved_at_60[0x20];
7349 
7350 	u8         table_type[0x8];
7351 	u8         reserved_at_88[0x18];
7352 
7353 	u8         reserved_at_a0[0x8];
7354 	u8         table_id[0x18];
7355 
7356 	u8         reserved_at_c0[0x140];
7357 };
7358 
7359 struct mlx5_ifc_destroy_flow_group_out_bits {
7360 	u8         status[0x8];
7361 	u8         reserved_at_8[0x18];
7362 
7363 	u8         syndrome[0x20];
7364 
7365 	u8         reserved_at_40[0x40];
7366 };
7367 
7368 struct mlx5_ifc_destroy_flow_group_in_bits {
7369 	u8         opcode[0x10];
7370 	u8         reserved_at_10[0x10];
7371 
7372 	u8         reserved_at_20[0x10];
7373 	u8         op_mod[0x10];
7374 
7375 	u8         other_vport[0x1];
7376 	u8         reserved_at_41[0xf];
7377 	u8         vport_number[0x10];
7378 
7379 	u8         reserved_at_60[0x20];
7380 
7381 	u8         table_type[0x8];
7382 	u8         reserved_at_88[0x18];
7383 
7384 	u8         reserved_at_a0[0x8];
7385 	u8         table_id[0x18];
7386 
7387 	u8         group_id[0x20];
7388 
7389 	u8         reserved_at_e0[0x120];
7390 };
7391 
7392 struct mlx5_ifc_destroy_eq_out_bits {
7393 	u8         status[0x8];
7394 	u8         reserved_at_8[0x18];
7395 
7396 	u8         syndrome[0x20];
7397 
7398 	u8         reserved_at_40[0x40];
7399 };
7400 
7401 struct mlx5_ifc_destroy_eq_in_bits {
7402 	u8         opcode[0x10];
7403 	u8         reserved_at_10[0x10];
7404 
7405 	u8         reserved_at_20[0x10];
7406 	u8         op_mod[0x10];
7407 
7408 	u8         reserved_at_40[0x18];
7409 	u8         eq_number[0x8];
7410 
7411 	u8         reserved_at_60[0x20];
7412 };
7413 
7414 struct mlx5_ifc_destroy_dct_out_bits {
7415 	u8         status[0x8];
7416 	u8         reserved_at_8[0x18];
7417 
7418 	u8         syndrome[0x20];
7419 
7420 	u8         reserved_at_40[0x40];
7421 };
7422 
7423 struct mlx5_ifc_destroy_dct_in_bits {
7424 	u8         opcode[0x10];
7425 	u8         uid[0x10];
7426 
7427 	u8         reserved_at_20[0x10];
7428 	u8         op_mod[0x10];
7429 
7430 	u8         reserved_at_40[0x8];
7431 	u8         dctn[0x18];
7432 
7433 	u8         reserved_at_60[0x20];
7434 };
7435 
7436 struct mlx5_ifc_destroy_cq_out_bits {
7437 	u8         status[0x8];
7438 	u8         reserved_at_8[0x18];
7439 
7440 	u8         syndrome[0x20];
7441 
7442 	u8         reserved_at_40[0x40];
7443 };
7444 
7445 struct mlx5_ifc_destroy_cq_in_bits {
7446 	u8         opcode[0x10];
7447 	u8         uid[0x10];
7448 
7449 	u8         reserved_at_20[0x10];
7450 	u8         op_mod[0x10];
7451 
7452 	u8         reserved_at_40[0x8];
7453 	u8         cqn[0x18];
7454 
7455 	u8         reserved_at_60[0x20];
7456 };
7457 
7458 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7459 	u8         status[0x8];
7460 	u8         reserved_at_8[0x18];
7461 
7462 	u8         syndrome[0x20];
7463 
7464 	u8         reserved_at_40[0x40];
7465 };
7466 
7467 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7468 	u8         opcode[0x10];
7469 	u8         reserved_at_10[0x10];
7470 
7471 	u8         reserved_at_20[0x10];
7472 	u8         op_mod[0x10];
7473 
7474 	u8         reserved_at_40[0x20];
7475 
7476 	u8         reserved_at_60[0x10];
7477 	u8         vxlan_udp_port[0x10];
7478 };
7479 
7480 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7481 	u8         status[0x8];
7482 	u8         reserved_at_8[0x18];
7483 
7484 	u8         syndrome[0x20];
7485 
7486 	u8         reserved_at_40[0x40];
7487 };
7488 
7489 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7490 	u8         opcode[0x10];
7491 	u8         reserved_at_10[0x10];
7492 
7493 	u8         reserved_at_20[0x10];
7494 	u8         op_mod[0x10];
7495 
7496 	u8         reserved_at_40[0x60];
7497 
7498 	u8         reserved_at_a0[0x8];
7499 	u8         table_index[0x18];
7500 
7501 	u8         reserved_at_c0[0x140];
7502 };
7503 
7504 struct mlx5_ifc_delete_fte_out_bits {
7505 	u8         status[0x8];
7506 	u8         reserved_at_8[0x18];
7507 
7508 	u8         syndrome[0x20];
7509 
7510 	u8         reserved_at_40[0x40];
7511 };
7512 
7513 struct mlx5_ifc_delete_fte_in_bits {
7514 	u8         opcode[0x10];
7515 	u8         reserved_at_10[0x10];
7516 
7517 	u8         reserved_at_20[0x10];
7518 	u8         op_mod[0x10];
7519 
7520 	u8         other_vport[0x1];
7521 	u8         reserved_at_41[0xf];
7522 	u8         vport_number[0x10];
7523 
7524 	u8         reserved_at_60[0x20];
7525 
7526 	u8         table_type[0x8];
7527 	u8         reserved_at_88[0x18];
7528 
7529 	u8         reserved_at_a0[0x8];
7530 	u8         table_id[0x18];
7531 
7532 	u8         reserved_at_c0[0x40];
7533 
7534 	u8         flow_index[0x20];
7535 
7536 	u8         reserved_at_120[0xe0];
7537 };
7538 
7539 struct mlx5_ifc_dealloc_xrcd_out_bits {
7540 	u8         status[0x8];
7541 	u8         reserved_at_8[0x18];
7542 
7543 	u8         syndrome[0x20];
7544 
7545 	u8         reserved_at_40[0x40];
7546 };
7547 
7548 struct mlx5_ifc_dealloc_xrcd_in_bits {
7549 	u8         opcode[0x10];
7550 	u8         uid[0x10];
7551 
7552 	u8         reserved_at_20[0x10];
7553 	u8         op_mod[0x10];
7554 
7555 	u8         reserved_at_40[0x8];
7556 	u8         xrcd[0x18];
7557 
7558 	u8         reserved_at_60[0x20];
7559 };
7560 
7561 struct mlx5_ifc_dealloc_uar_out_bits {
7562 	u8         status[0x8];
7563 	u8         reserved_at_8[0x18];
7564 
7565 	u8         syndrome[0x20];
7566 
7567 	u8         reserved_at_40[0x40];
7568 };
7569 
7570 struct mlx5_ifc_dealloc_uar_in_bits {
7571 	u8         opcode[0x10];
7572 	u8         reserved_at_10[0x10];
7573 
7574 	u8         reserved_at_20[0x10];
7575 	u8         op_mod[0x10];
7576 
7577 	u8         reserved_at_40[0x8];
7578 	u8         uar[0x18];
7579 
7580 	u8         reserved_at_60[0x20];
7581 };
7582 
7583 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7584 	u8         status[0x8];
7585 	u8         reserved_at_8[0x18];
7586 
7587 	u8         syndrome[0x20];
7588 
7589 	u8         reserved_at_40[0x40];
7590 };
7591 
7592 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7593 	u8         opcode[0x10];
7594 	u8         uid[0x10];
7595 
7596 	u8         reserved_at_20[0x10];
7597 	u8         op_mod[0x10];
7598 
7599 	u8         reserved_at_40[0x8];
7600 	u8         transport_domain[0x18];
7601 
7602 	u8         reserved_at_60[0x20];
7603 };
7604 
7605 struct mlx5_ifc_dealloc_q_counter_out_bits {
7606 	u8         status[0x8];
7607 	u8         reserved_at_8[0x18];
7608 
7609 	u8         syndrome[0x20];
7610 
7611 	u8         reserved_at_40[0x40];
7612 };
7613 
7614 struct mlx5_ifc_dealloc_q_counter_in_bits {
7615 	u8         opcode[0x10];
7616 	u8         reserved_at_10[0x10];
7617 
7618 	u8         reserved_at_20[0x10];
7619 	u8         op_mod[0x10];
7620 
7621 	u8         reserved_at_40[0x18];
7622 	u8         counter_set_id[0x8];
7623 
7624 	u8         reserved_at_60[0x20];
7625 };
7626 
7627 struct mlx5_ifc_dealloc_pd_out_bits {
7628 	u8         status[0x8];
7629 	u8         reserved_at_8[0x18];
7630 
7631 	u8         syndrome[0x20];
7632 
7633 	u8         reserved_at_40[0x40];
7634 };
7635 
7636 struct mlx5_ifc_dealloc_pd_in_bits {
7637 	u8         opcode[0x10];
7638 	u8         uid[0x10];
7639 
7640 	u8         reserved_at_20[0x10];
7641 	u8         op_mod[0x10];
7642 
7643 	u8         reserved_at_40[0x8];
7644 	u8         pd[0x18];
7645 
7646 	u8         reserved_at_60[0x20];
7647 };
7648 
7649 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7650 	u8         status[0x8];
7651 	u8         reserved_at_8[0x18];
7652 
7653 	u8         syndrome[0x20];
7654 
7655 	u8         reserved_at_40[0x40];
7656 };
7657 
7658 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7659 	u8         opcode[0x10];
7660 	u8         reserved_at_10[0x10];
7661 
7662 	u8         reserved_at_20[0x10];
7663 	u8         op_mod[0x10];
7664 
7665 	u8         flow_counter_id[0x20];
7666 
7667 	u8         reserved_at_60[0x20];
7668 };
7669 
7670 struct mlx5_ifc_create_xrq_out_bits {
7671 	u8         status[0x8];
7672 	u8         reserved_at_8[0x18];
7673 
7674 	u8         syndrome[0x20];
7675 
7676 	u8         reserved_at_40[0x8];
7677 	u8         xrqn[0x18];
7678 
7679 	u8         reserved_at_60[0x20];
7680 };
7681 
7682 struct mlx5_ifc_create_xrq_in_bits {
7683 	u8         opcode[0x10];
7684 	u8         uid[0x10];
7685 
7686 	u8         reserved_at_20[0x10];
7687 	u8         op_mod[0x10];
7688 
7689 	u8         reserved_at_40[0x40];
7690 
7691 	struct mlx5_ifc_xrqc_bits xrq_context;
7692 };
7693 
7694 struct mlx5_ifc_create_xrc_srq_out_bits {
7695 	u8         status[0x8];
7696 	u8         reserved_at_8[0x18];
7697 
7698 	u8         syndrome[0x20];
7699 
7700 	u8         reserved_at_40[0x8];
7701 	u8         xrc_srqn[0x18];
7702 
7703 	u8         reserved_at_60[0x20];
7704 };
7705 
7706 struct mlx5_ifc_create_xrc_srq_in_bits {
7707 	u8         opcode[0x10];
7708 	u8         uid[0x10];
7709 
7710 	u8         reserved_at_20[0x10];
7711 	u8         op_mod[0x10];
7712 
7713 	u8         reserved_at_40[0x40];
7714 
7715 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7716 
7717 	u8         reserved_at_280[0x60];
7718 
7719 	u8         xrc_srq_umem_valid[0x1];
7720 	u8         reserved_at_2e1[0x1f];
7721 
7722 	u8         reserved_at_300[0x580];
7723 
7724 	u8         pas[][0x40];
7725 };
7726 
7727 struct mlx5_ifc_create_tis_out_bits {
7728 	u8         status[0x8];
7729 	u8         reserved_at_8[0x18];
7730 
7731 	u8         syndrome[0x20];
7732 
7733 	u8         reserved_at_40[0x8];
7734 	u8         tisn[0x18];
7735 
7736 	u8         reserved_at_60[0x20];
7737 };
7738 
7739 struct mlx5_ifc_create_tis_in_bits {
7740 	u8         opcode[0x10];
7741 	u8         uid[0x10];
7742 
7743 	u8         reserved_at_20[0x10];
7744 	u8         op_mod[0x10];
7745 
7746 	u8         reserved_at_40[0xc0];
7747 
7748 	struct mlx5_ifc_tisc_bits ctx;
7749 };
7750 
7751 struct mlx5_ifc_create_tir_out_bits {
7752 	u8         status[0x8];
7753 	u8         icm_address_63_40[0x18];
7754 
7755 	u8         syndrome[0x20];
7756 
7757 	u8         icm_address_39_32[0x8];
7758 	u8         tirn[0x18];
7759 
7760 	u8         icm_address_31_0[0x20];
7761 };
7762 
7763 struct mlx5_ifc_create_tir_in_bits {
7764 	u8         opcode[0x10];
7765 	u8         uid[0x10];
7766 
7767 	u8         reserved_at_20[0x10];
7768 	u8         op_mod[0x10];
7769 
7770 	u8         reserved_at_40[0xc0];
7771 
7772 	struct mlx5_ifc_tirc_bits ctx;
7773 };
7774 
7775 struct mlx5_ifc_create_srq_out_bits {
7776 	u8         status[0x8];
7777 	u8         reserved_at_8[0x18];
7778 
7779 	u8         syndrome[0x20];
7780 
7781 	u8         reserved_at_40[0x8];
7782 	u8         srqn[0x18];
7783 
7784 	u8         reserved_at_60[0x20];
7785 };
7786 
7787 struct mlx5_ifc_create_srq_in_bits {
7788 	u8         opcode[0x10];
7789 	u8         uid[0x10];
7790 
7791 	u8         reserved_at_20[0x10];
7792 	u8         op_mod[0x10];
7793 
7794 	u8         reserved_at_40[0x40];
7795 
7796 	struct mlx5_ifc_srqc_bits srq_context_entry;
7797 
7798 	u8         reserved_at_280[0x600];
7799 
7800 	u8         pas[][0x40];
7801 };
7802 
7803 struct mlx5_ifc_create_sq_out_bits {
7804 	u8         status[0x8];
7805 	u8         reserved_at_8[0x18];
7806 
7807 	u8         syndrome[0x20];
7808 
7809 	u8         reserved_at_40[0x8];
7810 	u8         sqn[0x18];
7811 
7812 	u8         reserved_at_60[0x20];
7813 };
7814 
7815 struct mlx5_ifc_create_sq_in_bits {
7816 	u8         opcode[0x10];
7817 	u8         uid[0x10];
7818 
7819 	u8         reserved_at_20[0x10];
7820 	u8         op_mod[0x10];
7821 
7822 	u8         reserved_at_40[0xc0];
7823 
7824 	struct mlx5_ifc_sqc_bits ctx;
7825 };
7826 
7827 struct mlx5_ifc_create_scheduling_element_out_bits {
7828 	u8         status[0x8];
7829 	u8         reserved_at_8[0x18];
7830 
7831 	u8         syndrome[0x20];
7832 
7833 	u8         reserved_at_40[0x40];
7834 
7835 	u8         scheduling_element_id[0x20];
7836 
7837 	u8         reserved_at_a0[0x160];
7838 };
7839 
7840 struct mlx5_ifc_create_scheduling_element_in_bits {
7841 	u8         opcode[0x10];
7842 	u8         reserved_at_10[0x10];
7843 
7844 	u8         reserved_at_20[0x10];
7845 	u8         op_mod[0x10];
7846 
7847 	u8         scheduling_hierarchy[0x8];
7848 	u8         reserved_at_48[0x18];
7849 
7850 	u8         reserved_at_60[0xa0];
7851 
7852 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7853 
7854 	u8         reserved_at_300[0x100];
7855 };
7856 
7857 struct mlx5_ifc_create_rqt_out_bits {
7858 	u8         status[0x8];
7859 	u8         reserved_at_8[0x18];
7860 
7861 	u8         syndrome[0x20];
7862 
7863 	u8         reserved_at_40[0x8];
7864 	u8         rqtn[0x18];
7865 
7866 	u8         reserved_at_60[0x20];
7867 };
7868 
7869 struct mlx5_ifc_create_rqt_in_bits {
7870 	u8         opcode[0x10];
7871 	u8         uid[0x10];
7872 
7873 	u8         reserved_at_20[0x10];
7874 	u8         op_mod[0x10];
7875 
7876 	u8         reserved_at_40[0xc0];
7877 
7878 	struct mlx5_ifc_rqtc_bits rqt_context;
7879 };
7880 
7881 struct mlx5_ifc_create_rq_out_bits {
7882 	u8         status[0x8];
7883 	u8         reserved_at_8[0x18];
7884 
7885 	u8         syndrome[0x20];
7886 
7887 	u8         reserved_at_40[0x8];
7888 	u8         rqn[0x18];
7889 
7890 	u8         reserved_at_60[0x20];
7891 };
7892 
7893 struct mlx5_ifc_create_rq_in_bits {
7894 	u8         opcode[0x10];
7895 	u8         uid[0x10];
7896 
7897 	u8         reserved_at_20[0x10];
7898 	u8         op_mod[0x10];
7899 
7900 	u8         reserved_at_40[0xc0];
7901 
7902 	struct mlx5_ifc_rqc_bits ctx;
7903 };
7904 
7905 struct mlx5_ifc_create_rmp_out_bits {
7906 	u8         status[0x8];
7907 	u8         reserved_at_8[0x18];
7908 
7909 	u8         syndrome[0x20];
7910 
7911 	u8         reserved_at_40[0x8];
7912 	u8         rmpn[0x18];
7913 
7914 	u8         reserved_at_60[0x20];
7915 };
7916 
7917 struct mlx5_ifc_create_rmp_in_bits {
7918 	u8         opcode[0x10];
7919 	u8         uid[0x10];
7920 
7921 	u8         reserved_at_20[0x10];
7922 	u8         op_mod[0x10];
7923 
7924 	u8         reserved_at_40[0xc0];
7925 
7926 	struct mlx5_ifc_rmpc_bits ctx;
7927 };
7928 
7929 struct mlx5_ifc_create_qp_out_bits {
7930 	u8         status[0x8];
7931 	u8         reserved_at_8[0x18];
7932 
7933 	u8         syndrome[0x20];
7934 
7935 	u8         reserved_at_40[0x8];
7936 	u8         qpn[0x18];
7937 
7938 	u8         ece[0x20];
7939 };
7940 
7941 struct mlx5_ifc_create_qp_in_bits {
7942 	u8         opcode[0x10];
7943 	u8         uid[0x10];
7944 
7945 	u8         reserved_at_20[0x10];
7946 	u8         op_mod[0x10];
7947 
7948 	u8         reserved_at_40[0x8];
7949 	u8         input_qpn[0x18];
7950 
7951 	u8         reserved_at_60[0x20];
7952 	u8         opt_param_mask[0x20];
7953 
7954 	u8         ece[0x20];
7955 
7956 	struct mlx5_ifc_qpc_bits qpc;
7957 
7958 	u8         reserved_at_800[0x60];
7959 
7960 	u8         wq_umem_valid[0x1];
7961 	u8         reserved_at_861[0x1f];
7962 
7963 	u8         pas[][0x40];
7964 };
7965 
7966 struct mlx5_ifc_create_psv_out_bits {
7967 	u8         status[0x8];
7968 	u8         reserved_at_8[0x18];
7969 
7970 	u8         syndrome[0x20];
7971 
7972 	u8         reserved_at_40[0x40];
7973 
7974 	u8         reserved_at_80[0x8];
7975 	u8         psv0_index[0x18];
7976 
7977 	u8         reserved_at_a0[0x8];
7978 	u8         psv1_index[0x18];
7979 
7980 	u8         reserved_at_c0[0x8];
7981 	u8         psv2_index[0x18];
7982 
7983 	u8         reserved_at_e0[0x8];
7984 	u8         psv3_index[0x18];
7985 };
7986 
7987 struct mlx5_ifc_create_psv_in_bits {
7988 	u8         opcode[0x10];
7989 	u8         reserved_at_10[0x10];
7990 
7991 	u8         reserved_at_20[0x10];
7992 	u8         op_mod[0x10];
7993 
7994 	u8         num_psv[0x4];
7995 	u8         reserved_at_44[0x4];
7996 	u8         pd[0x18];
7997 
7998 	u8         reserved_at_60[0x20];
7999 };
8000 
8001 struct mlx5_ifc_create_mkey_out_bits {
8002 	u8         status[0x8];
8003 	u8         reserved_at_8[0x18];
8004 
8005 	u8         syndrome[0x20];
8006 
8007 	u8         reserved_at_40[0x8];
8008 	u8         mkey_index[0x18];
8009 
8010 	u8         reserved_at_60[0x20];
8011 };
8012 
8013 struct mlx5_ifc_create_mkey_in_bits {
8014 	u8         opcode[0x10];
8015 	u8         uid[0x10];
8016 
8017 	u8         reserved_at_20[0x10];
8018 	u8         op_mod[0x10];
8019 
8020 	u8         reserved_at_40[0x20];
8021 
8022 	u8         pg_access[0x1];
8023 	u8         mkey_umem_valid[0x1];
8024 	u8         reserved_at_62[0x1e];
8025 
8026 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8027 
8028 	u8         reserved_at_280[0x80];
8029 
8030 	u8         translations_octword_actual_size[0x20];
8031 
8032 	u8         reserved_at_320[0x560];
8033 
8034 	u8         klm_pas_mtt[][0x20];
8035 };
8036 
8037 enum {
8038 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
8039 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
8040 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
8041 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
8042 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
8043 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
8044 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
8045 };
8046 
8047 struct mlx5_ifc_create_flow_table_out_bits {
8048 	u8         status[0x8];
8049 	u8         icm_address_63_40[0x18];
8050 
8051 	u8         syndrome[0x20];
8052 
8053 	u8         icm_address_39_32[0x8];
8054 	u8         table_id[0x18];
8055 
8056 	u8         icm_address_31_0[0x20];
8057 };
8058 
8059 struct mlx5_ifc_create_flow_table_in_bits {
8060 	u8         opcode[0x10];
8061 	u8         reserved_at_10[0x10];
8062 
8063 	u8         reserved_at_20[0x10];
8064 	u8         op_mod[0x10];
8065 
8066 	u8         other_vport[0x1];
8067 	u8         reserved_at_41[0xf];
8068 	u8         vport_number[0x10];
8069 
8070 	u8         reserved_at_60[0x20];
8071 
8072 	u8         table_type[0x8];
8073 	u8         reserved_at_88[0x18];
8074 
8075 	u8         reserved_at_a0[0x20];
8076 
8077 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8078 };
8079 
8080 struct mlx5_ifc_create_flow_group_out_bits {
8081 	u8         status[0x8];
8082 	u8         reserved_at_8[0x18];
8083 
8084 	u8         syndrome[0x20];
8085 
8086 	u8         reserved_at_40[0x8];
8087 	u8         group_id[0x18];
8088 
8089 	u8         reserved_at_60[0x20];
8090 };
8091 
8092 enum {
8093 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8094 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8095 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8096 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8097 };
8098 
8099 struct mlx5_ifc_create_flow_group_in_bits {
8100 	u8         opcode[0x10];
8101 	u8         reserved_at_10[0x10];
8102 
8103 	u8         reserved_at_20[0x10];
8104 	u8         op_mod[0x10];
8105 
8106 	u8         other_vport[0x1];
8107 	u8         reserved_at_41[0xf];
8108 	u8         vport_number[0x10];
8109 
8110 	u8         reserved_at_60[0x20];
8111 
8112 	u8         table_type[0x8];
8113 	u8         reserved_at_88[0x18];
8114 
8115 	u8         reserved_at_a0[0x8];
8116 	u8         table_id[0x18];
8117 
8118 	u8         source_eswitch_owner_vhca_id_valid[0x1];
8119 
8120 	u8         reserved_at_c1[0x1f];
8121 
8122 	u8         start_flow_index[0x20];
8123 
8124 	u8         reserved_at_100[0x20];
8125 
8126 	u8         end_flow_index[0x20];
8127 
8128 	u8         reserved_at_140[0xa0];
8129 
8130 	u8         reserved_at_1e0[0x18];
8131 	u8         match_criteria_enable[0x8];
8132 
8133 	struct mlx5_ifc_fte_match_param_bits match_criteria;
8134 
8135 	u8         reserved_at_1200[0xe00];
8136 };
8137 
8138 struct mlx5_ifc_create_eq_out_bits {
8139 	u8         status[0x8];
8140 	u8         reserved_at_8[0x18];
8141 
8142 	u8         syndrome[0x20];
8143 
8144 	u8         reserved_at_40[0x18];
8145 	u8         eq_number[0x8];
8146 
8147 	u8         reserved_at_60[0x20];
8148 };
8149 
8150 struct mlx5_ifc_create_eq_in_bits {
8151 	u8         opcode[0x10];
8152 	u8         uid[0x10];
8153 
8154 	u8         reserved_at_20[0x10];
8155 	u8         op_mod[0x10];
8156 
8157 	u8         reserved_at_40[0x40];
8158 
8159 	struct mlx5_ifc_eqc_bits eq_context_entry;
8160 
8161 	u8         reserved_at_280[0x40];
8162 
8163 	u8         event_bitmask[4][0x40];
8164 
8165 	u8         reserved_at_3c0[0x4c0];
8166 
8167 	u8         pas[][0x40];
8168 };
8169 
8170 struct mlx5_ifc_create_dct_out_bits {
8171 	u8         status[0x8];
8172 	u8         reserved_at_8[0x18];
8173 
8174 	u8         syndrome[0x20];
8175 
8176 	u8         reserved_at_40[0x8];
8177 	u8         dctn[0x18];
8178 
8179 	u8         ece[0x20];
8180 };
8181 
8182 struct mlx5_ifc_create_dct_in_bits {
8183 	u8         opcode[0x10];
8184 	u8         uid[0x10];
8185 
8186 	u8         reserved_at_20[0x10];
8187 	u8         op_mod[0x10];
8188 
8189 	u8         reserved_at_40[0x40];
8190 
8191 	struct mlx5_ifc_dctc_bits dct_context_entry;
8192 
8193 	u8         reserved_at_280[0x180];
8194 };
8195 
8196 struct mlx5_ifc_create_cq_out_bits {
8197 	u8         status[0x8];
8198 	u8         reserved_at_8[0x18];
8199 
8200 	u8         syndrome[0x20];
8201 
8202 	u8         reserved_at_40[0x8];
8203 	u8         cqn[0x18];
8204 
8205 	u8         reserved_at_60[0x20];
8206 };
8207 
8208 struct mlx5_ifc_create_cq_in_bits {
8209 	u8         opcode[0x10];
8210 	u8         uid[0x10];
8211 
8212 	u8         reserved_at_20[0x10];
8213 	u8         op_mod[0x10];
8214 
8215 	u8         reserved_at_40[0x40];
8216 
8217 	struct mlx5_ifc_cqc_bits cq_context;
8218 
8219 	u8         reserved_at_280[0x60];
8220 
8221 	u8         cq_umem_valid[0x1];
8222 	u8         reserved_at_2e1[0x59f];
8223 
8224 	u8         pas[][0x40];
8225 };
8226 
8227 struct mlx5_ifc_config_int_moderation_out_bits {
8228 	u8         status[0x8];
8229 	u8         reserved_at_8[0x18];
8230 
8231 	u8         syndrome[0x20];
8232 
8233 	u8         reserved_at_40[0x4];
8234 	u8         min_delay[0xc];
8235 	u8         int_vector[0x10];
8236 
8237 	u8         reserved_at_60[0x20];
8238 };
8239 
8240 enum {
8241 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8242 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8243 };
8244 
8245 struct mlx5_ifc_config_int_moderation_in_bits {
8246 	u8         opcode[0x10];
8247 	u8         reserved_at_10[0x10];
8248 
8249 	u8         reserved_at_20[0x10];
8250 	u8         op_mod[0x10];
8251 
8252 	u8         reserved_at_40[0x4];
8253 	u8         min_delay[0xc];
8254 	u8         int_vector[0x10];
8255 
8256 	u8         reserved_at_60[0x20];
8257 };
8258 
8259 struct mlx5_ifc_attach_to_mcg_out_bits {
8260 	u8         status[0x8];
8261 	u8         reserved_at_8[0x18];
8262 
8263 	u8         syndrome[0x20];
8264 
8265 	u8         reserved_at_40[0x40];
8266 };
8267 
8268 struct mlx5_ifc_attach_to_mcg_in_bits {
8269 	u8         opcode[0x10];
8270 	u8         uid[0x10];
8271 
8272 	u8         reserved_at_20[0x10];
8273 	u8         op_mod[0x10];
8274 
8275 	u8         reserved_at_40[0x8];
8276 	u8         qpn[0x18];
8277 
8278 	u8         reserved_at_60[0x20];
8279 
8280 	u8         multicast_gid[16][0x8];
8281 };
8282 
8283 struct mlx5_ifc_arm_xrq_out_bits {
8284 	u8         status[0x8];
8285 	u8         reserved_at_8[0x18];
8286 
8287 	u8         syndrome[0x20];
8288 
8289 	u8         reserved_at_40[0x40];
8290 };
8291 
8292 struct mlx5_ifc_arm_xrq_in_bits {
8293 	u8         opcode[0x10];
8294 	u8         reserved_at_10[0x10];
8295 
8296 	u8         reserved_at_20[0x10];
8297 	u8         op_mod[0x10];
8298 
8299 	u8         reserved_at_40[0x8];
8300 	u8         xrqn[0x18];
8301 
8302 	u8         reserved_at_60[0x10];
8303 	u8         lwm[0x10];
8304 };
8305 
8306 struct mlx5_ifc_arm_xrc_srq_out_bits {
8307 	u8         status[0x8];
8308 	u8         reserved_at_8[0x18];
8309 
8310 	u8         syndrome[0x20];
8311 
8312 	u8         reserved_at_40[0x40];
8313 };
8314 
8315 enum {
8316 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8317 };
8318 
8319 struct mlx5_ifc_arm_xrc_srq_in_bits {
8320 	u8         opcode[0x10];
8321 	u8         uid[0x10];
8322 
8323 	u8         reserved_at_20[0x10];
8324 	u8         op_mod[0x10];
8325 
8326 	u8         reserved_at_40[0x8];
8327 	u8         xrc_srqn[0x18];
8328 
8329 	u8         reserved_at_60[0x10];
8330 	u8         lwm[0x10];
8331 };
8332 
8333 struct mlx5_ifc_arm_rq_out_bits {
8334 	u8         status[0x8];
8335 	u8         reserved_at_8[0x18];
8336 
8337 	u8         syndrome[0x20];
8338 
8339 	u8         reserved_at_40[0x40];
8340 };
8341 
8342 enum {
8343 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8344 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8345 };
8346 
8347 struct mlx5_ifc_arm_rq_in_bits {
8348 	u8         opcode[0x10];
8349 	u8         uid[0x10];
8350 
8351 	u8         reserved_at_20[0x10];
8352 	u8         op_mod[0x10];
8353 
8354 	u8         reserved_at_40[0x8];
8355 	u8         srq_number[0x18];
8356 
8357 	u8         reserved_at_60[0x10];
8358 	u8         lwm[0x10];
8359 };
8360 
8361 struct mlx5_ifc_arm_dct_out_bits {
8362 	u8         status[0x8];
8363 	u8         reserved_at_8[0x18];
8364 
8365 	u8         syndrome[0x20];
8366 
8367 	u8         reserved_at_40[0x40];
8368 };
8369 
8370 struct mlx5_ifc_arm_dct_in_bits {
8371 	u8         opcode[0x10];
8372 	u8         reserved_at_10[0x10];
8373 
8374 	u8         reserved_at_20[0x10];
8375 	u8         op_mod[0x10];
8376 
8377 	u8         reserved_at_40[0x8];
8378 	u8         dct_number[0x18];
8379 
8380 	u8         reserved_at_60[0x20];
8381 };
8382 
8383 struct mlx5_ifc_alloc_xrcd_out_bits {
8384 	u8         status[0x8];
8385 	u8         reserved_at_8[0x18];
8386 
8387 	u8         syndrome[0x20];
8388 
8389 	u8         reserved_at_40[0x8];
8390 	u8         xrcd[0x18];
8391 
8392 	u8         reserved_at_60[0x20];
8393 };
8394 
8395 struct mlx5_ifc_alloc_xrcd_in_bits {
8396 	u8         opcode[0x10];
8397 	u8         uid[0x10];
8398 
8399 	u8         reserved_at_20[0x10];
8400 	u8         op_mod[0x10];
8401 
8402 	u8         reserved_at_40[0x40];
8403 };
8404 
8405 struct mlx5_ifc_alloc_uar_out_bits {
8406 	u8         status[0x8];
8407 	u8         reserved_at_8[0x18];
8408 
8409 	u8         syndrome[0x20];
8410 
8411 	u8         reserved_at_40[0x8];
8412 	u8         uar[0x18];
8413 
8414 	u8         reserved_at_60[0x20];
8415 };
8416 
8417 struct mlx5_ifc_alloc_uar_in_bits {
8418 	u8         opcode[0x10];
8419 	u8         reserved_at_10[0x10];
8420 
8421 	u8         reserved_at_20[0x10];
8422 	u8         op_mod[0x10];
8423 
8424 	u8         reserved_at_40[0x40];
8425 };
8426 
8427 struct mlx5_ifc_alloc_transport_domain_out_bits {
8428 	u8         status[0x8];
8429 	u8         reserved_at_8[0x18];
8430 
8431 	u8         syndrome[0x20];
8432 
8433 	u8         reserved_at_40[0x8];
8434 	u8         transport_domain[0x18];
8435 
8436 	u8         reserved_at_60[0x20];
8437 };
8438 
8439 struct mlx5_ifc_alloc_transport_domain_in_bits {
8440 	u8         opcode[0x10];
8441 	u8         uid[0x10];
8442 
8443 	u8         reserved_at_20[0x10];
8444 	u8         op_mod[0x10];
8445 
8446 	u8         reserved_at_40[0x40];
8447 };
8448 
8449 struct mlx5_ifc_alloc_q_counter_out_bits {
8450 	u8         status[0x8];
8451 	u8         reserved_at_8[0x18];
8452 
8453 	u8         syndrome[0x20];
8454 
8455 	u8         reserved_at_40[0x18];
8456 	u8         counter_set_id[0x8];
8457 
8458 	u8         reserved_at_60[0x20];
8459 };
8460 
8461 struct mlx5_ifc_alloc_q_counter_in_bits {
8462 	u8         opcode[0x10];
8463 	u8         uid[0x10];
8464 
8465 	u8         reserved_at_20[0x10];
8466 	u8         op_mod[0x10];
8467 
8468 	u8         reserved_at_40[0x40];
8469 };
8470 
8471 struct mlx5_ifc_alloc_pd_out_bits {
8472 	u8         status[0x8];
8473 	u8         reserved_at_8[0x18];
8474 
8475 	u8         syndrome[0x20];
8476 
8477 	u8         reserved_at_40[0x8];
8478 	u8         pd[0x18];
8479 
8480 	u8         reserved_at_60[0x20];
8481 };
8482 
8483 struct mlx5_ifc_alloc_pd_in_bits {
8484 	u8         opcode[0x10];
8485 	u8         uid[0x10];
8486 
8487 	u8         reserved_at_20[0x10];
8488 	u8         op_mod[0x10];
8489 
8490 	u8         reserved_at_40[0x40];
8491 };
8492 
8493 struct mlx5_ifc_alloc_flow_counter_out_bits {
8494 	u8         status[0x8];
8495 	u8         reserved_at_8[0x18];
8496 
8497 	u8         syndrome[0x20];
8498 
8499 	u8         flow_counter_id[0x20];
8500 
8501 	u8         reserved_at_60[0x20];
8502 };
8503 
8504 struct mlx5_ifc_alloc_flow_counter_in_bits {
8505 	u8         opcode[0x10];
8506 	u8         reserved_at_10[0x10];
8507 
8508 	u8         reserved_at_20[0x10];
8509 	u8         op_mod[0x10];
8510 
8511 	u8         reserved_at_40[0x38];
8512 	u8         flow_counter_bulk[0x8];
8513 };
8514 
8515 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8516 	u8         status[0x8];
8517 	u8         reserved_at_8[0x18];
8518 
8519 	u8         syndrome[0x20];
8520 
8521 	u8         reserved_at_40[0x40];
8522 };
8523 
8524 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8525 	u8         opcode[0x10];
8526 	u8         reserved_at_10[0x10];
8527 
8528 	u8         reserved_at_20[0x10];
8529 	u8         op_mod[0x10];
8530 
8531 	u8         reserved_at_40[0x20];
8532 
8533 	u8         reserved_at_60[0x10];
8534 	u8         vxlan_udp_port[0x10];
8535 };
8536 
8537 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8538 	u8         status[0x8];
8539 	u8         reserved_at_8[0x18];
8540 
8541 	u8         syndrome[0x20];
8542 
8543 	u8         reserved_at_40[0x40];
8544 };
8545 
8546 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8547 	u8         rate_limit[0x20];
8548 
8549 	u8	   burst_upper_bound[0x20];
8550 
8551 	u8         reserved_at_40[0x10];
8552 	u8	   typical_packet_size[0x10];
8553 
8554 	u8         reserved_at_60[0x120];
8555 };
8556 
8557 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8558 	u8         opcode[0x10];
8559 	u8         uid[0x10];
8560 
8561 	u8         reserved_at_20[0x10];
8562 	u8         op_mod[0x10];
8563 
8564 	u8         reserved_at_40[0x10];
8565 	u8         rate_limit_index[0x10];
8566 
8567 	u8         reserved_at_60[0x20];
8568 
8569 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8570 };
8571 
8572 struct mlx5_ifc_access_register_out_bits {
8573 	u8         status[0x8];
8574 	u8         reserved_at_8[0x18];
8575 
8576 	u8         syndrome[0x20];
8577 
8578 	u8         reserved_at_40[0x40];
8579 
8580 	u8         register_data[][0x20];
8581 };
8582 
8583 enum {
8584 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8585 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8586 };
8587 
8588 struct mlx5_ifc_access_register_in_bits {
8589 	u8         opcode[0x10];
8590 	u8         reserved_at_10[0x10];
8591 
8592 	u8         reserved_at_20[0x10];
8593 	u8         op_mod[0x10];
8594 
8595 	u8         reserved_at_40[0x10];
8596 	u8         register_id[0x10];
8597 
8598 	u8         argument[0x20];
8599 
8600 	u8         register_data[][0x20];
8601 };
8602 
8603 struct mlx5_ifc_sltp_reg_bits {
8604 	u8         status[0x4];
8605 	u8         version[0x4];
8606 	u8         local_port[0x8];
8607 	u8         pnat[0x2];
8608 	u8         reserved_at_12[0x2];
8609 	u8         lane[0x4];
8610 	u8         reserved_at_18[0x8];
8611 
8612 	u8         reserved_at_20[0x20];
8613 
8614 	u8         reserved_at_40[0x7];
8615 	u8         polarity[0x1];
8616 	u8         ob_tap0[0x8];
8617 	u8         ob_tap1[0x8];
8618 	u8         ob_tap2[0x8];
8619 
8620 	u8         reserved_at_60[0xc];
8621 	u8         ob_preemp_mode[0x4];
8622 	u8         ob_reg[0x8];
8623 	u8         ob_bias[0x8];
8624 
8625 	u8         reserved_at_80[0x20];
8626 };
8627 
8628 struct mlx5_ifc_slrg_reg_bits {
8629 	u8         status[0x4];
8630 	u8         version[0x4];
8631 	u8         local_port[0x8];
8632 	u8         pnat[0x2];
8633 	u8         reserved_at_12[0x2];
8634 	u8         lane[0x4];
8635 	u8         reserved_at_18[0x8];
8636 
8637 	u8         time_to_link_up[0x10];
8638 	u8         reserved_at_30[0xc];
8639 	u8         grade_lane_speed[0x4];
8640 
8641 	u8         grade_version[0x8];
8642 	u8         grade[0x18];
8643 
8644 	u8         reserved_at_60[0x4];
8645 	u8         height_grade_type[0x4];
8646 	u8         height_grade[0x18];
8647 
8648 	u8         height_dz[0x10];
8649 	u8         height_dv[0x10];
8650 
8651 	u8         reserved_at_a0[0x10];
8652 	u8         height_sigma[0x10];
8653 
8654 	u8         reserved_at_c0[0x20];
8655 
8656 	u8         reserved_at_e0[0x4];
8657 	u8         phase_grade_type[0x4];
8658 	u8         phase_grade[0x18];
8659 
8660 	u8         reserved_at_100[0x8];
8661 	u8         phase_eo_pos[0x8];
8662 	u8         reserved_at_110[0x8];
8663 	u8         phase_eo_neg[0x8];
8664 
8665 	u8         ffe_set_tested[0x10];
8666 	u8         test_errors_per_lane[0x10];
8667 };
8668 
8669 struct mlx5_ifc_pvlc_reg_bits {
8670 	u8         reserved_at_0[0x8];
8671 	u8         local_port[0x8];
8672 	u8         reserved_at_10[0x10];
8673 
8674 	u8         reserved_at_20[0x1c];
8675 	u8         vl_hw_cap[0x4];
8676 
8677 	u8         reserved_at_40[0x1c];
8678 	u8         vl_admin[0x4];
8679 
8680 	u8         reserved_at_60[0x1c];
8681 	u8         vl_operational[0x4];
8682 };
8683 
8684 struct mlx5_ifc_pude_reg_bits {
8685 	u8         swid[0x8];
8686 	u8         local_port[0x8];
8687 	u8         reserved_at_10[0x4];
8688 	u8         admin_status[0x4];
8689 	u8         reserved_at_18[0x4];
8690 	u8         oper_status[0x4];
8691 
8692 	u8         reserved_at_20[0x60];
8693 };
8694 
8695 struct mlx5_ifc_ptys_reg_bits {
8696 	u8         reserved_at_0[0x1];
8697 	u8         an_disable_admin[0x1];
8698 	u8         an_disable_cap[0x1];
8699 	u8         reserved_at_3[0x5];
8700 	u8         local_port[0x8];
8701 	u8         reserved_at_10[0xd];
8702 	u8         proto_mask[0x3];
8703 
8704 	u8         an_status[0x4];
8705 	u8         reserved_at_24[0xc];
8706 	u8         data_rate_oper[0x10];
8707 
8708 	u8         ext_eth_proto_capability[0x20];
8709 
8710 	u8         eth_proto_capability[0x20];
8711 
8712 	u8         ib_link_width_capability[0x10];
8713 	u8         ib_proto_capability[0x10];
8714 
8715 	u8         ext_eth_proto_admin[0x20];
8716 
8717 	u8         eth_proto_admin[0x20];
8718 
8719 	u8         ib_link_width_admin[0x10];
8720 	u8         ib_proto_admin[0x10];
8721 
8722 	u8         ext_eth_proto_oper[0x20];
8723 
8724 	u8         eth_proto_oper[0x20];
8725 
8726 	u8         ib_link_width_oper[0x10];
8727 	u8         ib_proto_oper[0x10];
8728 
8729 	u8         reserved_at_160[0x1c];
8730 	u8         connector_type[0x4];
8731 
8732 	u8         eth_proto_lp_advertise[0x20];
8733 
8734 	u8         reserved_at_1a0[0x60];
8735 };
8736 
8737 struct mlx5_ifc_mlcr_reg_bits {
8738 	u8         reserved_at_0[0x8];
8739 	u8         local_port[0x8];
8740 	u8         reserved_at_10[0x20];
8741 
8742 	u8         beacon_duration[0x10];
8743 	u8         reserved_at_40[0x10];
8744 
8745 	u8         beacon_remain[0x10];
8746 };
8747 
8748 struct mlx5_ifc_ptas_reg_bits {
8749 	u8         reserved_at_0[0x20];
8750 
8751 	u8         algorithm_options[0x10];
8752 	u8         reserved_at_30[0x4];
8753 	u8         repetitions_mode[0x4];
8754 	u8         num_of_repetitions[0x8];
8755 
8756 	u8         grade_version[0x8];
8757 	u8         height_grade_type[0x4];
8758 	u8         phase_grade_type[0x4];
8759 	u8         height_grade_weight[0x8];
8760 	u8         phase_grade_weight[0x8];
8761 
8762 	u8         gisim_measure_bits[0x10];
8763 	u8         adaptive_tap_measure_bits[0x10];
8764 
8765 	u8         ber_bath_high_error_threshold[0x10];
8766 	u8         ber_bath_mid_error_threshold[0x10];
8767 
8768 	u8         ber_bath_low_error_threshold[0x10];
8769 	u8         one_ratio_high_threshold[0x10];
8770 
8771 	u8         one_ratio_high_mid_threshold[0x10];
8772 	u8         one_ratio_low_mid_threshold[0x10];
8773 
8774 	u8         one_ratio_low_threshold[0x10];
8775 	u8         ndeo_error_threshold[0x10];
8776 
8777 	u8         mixer_offset_step_size[0x10];
8778 	u8         reserved_at_110[0x8];
8779 	u8         mix90_phase_for_voltage_bath[0x8];
8780 
8781 	u8         mixer_offset_start[0x10];
8782 	u8         mixer_offset_end[0x10];
8783 
8784 	u8         reserved_at_140[0x15];
8785 	u8         ber_test_time[0xb];
8786 };
8787 
8788 struct mlx5_ifc_pspa_reg_bits {
8789 	u8         swid[0x8];
8790 	u8         local_port[0x8];
8791 	u8         sub_port[0x8];
8792 	u8         reserved_at_18[0x8];
8793 
8794 	u8         reserved_at_20[0x20];
8795 };
8796 
8797 struct mlx5_ifc_pqdr_reg_bits {
8798 	u8         reserved_at_0[0x8];
8799 	u8         local_port[0x8];
8800 	u8         reserved_at_10[0x5];
8801 	u8         prio[0x3];
8802 	u8         reserved_at_18[0x6];
8803 	u8         mode[0x2];
8804 
8805 	u8         reserved_at_20[0x20];
8806 
8807 	u8         reserved_at_40[0x10];
8808 	u8         min_threshold[0x10];
8809 
8810 	u8         reserved_at_60[0x10];
8811 	u8         max_threshold[0x10];
8812 
8813 	u8         reserved_at_80[0x10];
8814 	u8         mark_probability_denominator[0x10];
8815 
8816 	u8         reserved_at_a0[0x60];
8817 };
8818 
8819 struct mlx5_ifc_ppsc_reg_bits {
8820 	u8         reserved_at_0[0x8];
8821 	u8         local_port[0x8];
8822 	u8         reserved_at_10[0x10];
8823 
8824 	u8         reserved_at_20[0x60];
8825 
8826 	u8         reserved_at_80[0x1c];
8827 	u8         wrps_admin[0x4];
8828 
8829 	u8         reserved_at_a0[0x1c];
8830 	u8         wrps_status[0x4];
8831 
8832 	u8         reserved_at_c0[0x8];
8833 	u8         up_threshold[0x8];
8834 	u8         reserved_at_d0[0x8];
8835 	u8         down_threshold[0x8];
8836 
8837 	u8         reserved_at_e0[0x20];
8838 
8839 	u8         reserved_at_100[0x1c];
8840 	u8         srps_admin[0x4];
8841 
8842 	u8         reserved_at_120[0x1c];
8843 	u8         srps_status[0x4];
8844 
8845 	u8         reserved_at_140[0x40];
8846 };
8847 
8848 struct mlx5_ifc_pplr_reg_bits {
8849 	u8         reserved_at_0[0x8];
8850 	u8         local_port[0x8];
8851 	u8         reserved_at_10[0x10];
8852 
8853 	u8         reserved_at_20[0x8];
8854 	u8         lb_cap[0x8];
8855 	u8         reserved_at_30[0x8];
8856 	u8         lb_en[0x8];
8857 };
8858 
8859 struct mlx5_ifc_pplm_reg_bits {
8860 	u8         reserved_at_0[0x8];
8861 	u8	   local_port[0x8];
8862 	u8	   reserved_at_10[0x10];
8863 
8864 	u8	   reserved_at_20[0x20];
8865 
8866 	u8	   port_profile_mode[0x8];
8867 	u8	   static_port_profile[0x8];
8868 	u8	   active_port_profile[0x8];
8869 	u8	   reserved_at_58[0x8];
8870 
8871 	u8	   retransmission_active[0x8];
8872 	u8	   fec_mode_active[0x18];
8873 
8874 	u8	   rs_fec_correction_bypass_cap[0x4];
8875 	u8	   reserved_at_84[0x8];
8876 	u8	   fec_override_cap_56g[0x4];
8877 	u8	   fec_override_cap_100g[0x4];
8878 	u8	   fec_override_cap_50g[0x4];
8879 	u8	   fec_override_cap_25g[0x4];
8880 	u8	   fec_override_cap_10g_40g[0x4];
8881 
8882 	u8	   rs_fec_correction_bypass_admin[0x4];
8883 	u8	   reserved_at_a4[0x8];
8884 	u8	   fec_override_admin_56g[0x4];
8885 	u8	   fec_override_admin_100g[0x4];
8886 	u8	   fec_override_admin_50g[0x4];
8887 	u8	   fec_override_admin_25g[0x4];
8888 	u8	   fec_override_admin_10g_40g[0x4];
8889 
8890 	u8         fec_override_cap_400g_8x[0x10];
8891 	u8         fec_override_cap_200g_4x[0x10];
8892 
8893 	u8         fec_override_cap_100g_2x[0x10];
8894 	u8         fec_override_cap_50g_1x[0x10];
8895 
8896 	u8         fec_override_admin_400g_8x[0x10];
8897 	u8         fec_override_admin_200g_4x[0x10];
8898 
8899 	u8         fec_override_admin_100g_2x[0x10];
8900 	u8         fec_override_admin_50g_1x[0x10];
8901 
8902 	u8         reserved_at_140[0x140];
8903 };
8904 
8905 struct mlx5_ifc_ppcnt_reg_bits {
8906 	u8         swid[0x8];
8907 	u8         local_port[0x8];
8908 	u8         pnat[0x2];
8909 	u8         reserved_at_12[0x8];
8910 	u8         grp[0x6];
8911 
8912 	u8         clr[0x1];
8913 	u8         reserved_at_21[0x1c];
8914 	u8         prio_tc[0x3];
8915 
8916 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8917 };
8918 
8919 struct mlx5_ifc_mpein_reg_bits {
8920 	u8         reserved_at_0[0x2];
8921 	u8         depth[0x6];
8922 	u8         pcie_index[0x8];
8923 	u8         node[0x8];
8924 	u8         reserved_at_18[0x8];
8925 
8926 	u8         capability_mask[0x20];
8927 
8928 	u8         reserved_at_40[0x8];
8929 	u8         link_width_enabled[0x8];
8930 	u8         link_speed_enabled[0x10];
8931 
8932 	u8         lane0_physical_position[0x8];
8933 	u8         link_width_active[0x8];
8934 	u8         link_speed_active[0x10];
8935 
8936 	u8         num_of_pfs[0x10];
8937 	u8         num_of_vfs[0x10];
8938 
8939 	u8         bdf0[0x10];
8940 	u8         reserved_at_b0[0x10];
8941 
8942 	u8         max_read_request_size[0x4];
8943 	u8         max_payload_size[0x4];
8944 	u8         reserved_at_c8[0x5];
8945 	u8         pwr_status[0x3];
8946 	u8         port_type[0x4];
8947 	u8         reserved_at_d4[0xb];
8948 	u8         lane_reversal[0x1];
8949 
8950 	u8         reserved_at_e0[0x14];
8951 	u8         pci_power[0xc];
8952 
8953 	u8         reserved_at_100[0x20];
8954 
8955 	u8         device_status[0x10];
8956 	u8         port_state[0x8];
8957 	u8         reserved_at_138[0x8];
8958 
8959 	u8         reserved_at_140[0x10];
8960 	u8         receiver_detect_result[0x10];
8961 
8962 	u8         reserved_at_160[0x20];
8963 };
8964 
8965 struct mlx5_ifc_mpcnt_reg_bits {
8966 	u8         reserved_at_0[0x8];
8967 	u8         pcie_index[0x8];
8968 	u8         reserved_at_10[0xa];
8969 	u8         grp[0x6];
8970 
8971 	u8         clr[0x1];
8972 	u8         reserved_at_21[0x1f];
8973 
8974 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8975 };
8976 
8977 struct mlx5_ifc_ppad_reg_bits {
8978 	u8         reserved_at_0[0x3];
8979 	u8         single_mac[0x1];
8980 	u8         reserved_at_4[0x4];
8981 	u8         local_port[0x8];
8982 	u8         mac_47_32[0x10];
8983 
8984 	u8         mac_31_0[0x20];
8985 
8986 	u8         reserved_at_40[0x40];
8987 };
8988 
8989 struct mlx5_ifc_pmtu_reg_bits {
8990 	u8         reserved_at_0[0x8];
8991 	u8         local_port[0x8];
8992 	u8         reserved_at_10[0x10];
8993 
8994 	u8         max_mtu[0x10];
8995 	u8         reserved_at_30[0x10];
8996 
8997 	u8         admin_mtu[0x10];
8998 	u8         reserved_at_50[0x10];
8999 
9000 	u8         oper_mtu[0x10];
9001 	u8         reserved_at_70[0x10];
9002 };
9003 
9004 struct mlx5_ifc_pmpr_reg_bits {
9005 	u8         reserved_at_0[0x8];
9006 	u8         module[0x8];
9007 	u8         reserved_at_10[0x10];
9008 
9009 	u8         reserved_at_20[0x18];
9010 	u8         attenuation_5g[0x8];
9011 
9012 	u8         reserved_at_40[0x18];
9013 	u8         attenuation_7g[0x8];
9014 
9015 	u8         reserved_at_60[0x18];
9016 	u8         attenuation_12g[0x8];
9017 };
9018 
9019 struct mlx5_ifc_pmpe_reg_bits {
9020 	u8         reserved_at_0[0x8];
9021 	u8         module[0x8];
9022 	u8         reserved_at_10[0xc];
9023 	u8         module_status[0x4];
9024 
9025 	u8         reserved_at_20[0x60];
9026 };
9027 
9028 struct mlx5_ifc_pmpc_reg_bits {
9029 	u8         module_state_updated[32][0x8];
9030 };
9031 
9032 struct mlx5_ifc_pmlpn_reg_bits {
9033 	u8         reserved_at_0[0x4];
9034 	u8         mlpn_status[0x4];
9035 	u8         local_port[0x8];
9036 	u8         reserved_at_10[0x10];
9037 
9038 	u8         e[0x1];
9039 	u8         reserved_at_21[0x1f];
9040 };
9041 
9042 struct mlx5_ifc_pmlp_reg_bits {
9043 	u8         rxtx[0x1];
9044 	u8         reserved_at_1[0x7];
9045 	u8         local_port[0x8];
9046 	u8         reserved_at_10[0x8];
9047 	u8         width[0x8];
9048 
9049 	u8         lane0_module_mapping[0x20];
9050 
9051 	u8         lane1_module_mapping[0x20];
9052 
9053 	u8         lane2_module_mapping[0x20];
9054 
9055 	u8         lane3_module_mapping[0x20];
9056 
9057 	u8         reserved_at_a0[0x160];
9058 };
9059 
9060 struct mlx5_ifc_pmaos_reg_bits {
9061 	u8         reserved_at_0[0x8];
9062 	u8         module[0x8];
9063 	u8         reserved_at_10[0x4];
9064 	u8         admin_status[0x4];
9065 	u8         reserved_at_18[0x4];
9066 	u8         oper_status[0x4];
9067 
9068 	u8         ase[0x1];
9069 	u8         ee[0x1];
9070 	u8         reserved_at_22[0x1c];
9071 	u8         e[0x2];
9072 
9073 	u8         reserved_at_40[0x40];
9074 };
9075 
9076 struct mlx5_ifc_plpc_reg_bits {
9077 	u8         reserved_at_0[0x4];
9078 	u8         profile_id[0xc];
9079 	u8         reserved_at_10[0x4];
9080 	u8         proto_mask[0x4];
9081 	u8         reserved_at_18[0x8];
9082 
9083 	u8         reserved_at_20[0x10];
9084 	u8         lane_speed[0x10];
9085 
9086 	u8         reserved_at_40[0x17];
9087 	u8         lpbf[0x1];
9088 	u8         fec_mode_policy[0x8];
9089 
9090 	u8         retransmission_capability[0x8];
9091 	u8         fec_mode_capability[0x18];
9092 
9093 	u8         retransmission_support_admin[0x8];
9094 	u8         fec_mode_support_admin[0x18];
9095 
9096 	u8         retransmission_request_admin[0x8];
9097 	u8         fec_mode_request_admin[0x18];
9098 
9099 	u8         reserved_at_c0[0x80];
9100 };
9101 
9102 struct mlx5_ifc_plib_reg_bits {
9103 	u8         reserved_at_0[0x8];
9104 	u8         local_port[0x8];
9105 	u8         reserved_at_10[0x8];
9106 	u8         ib_port[0x8];
9107 
9108 	u8         reserved_at_20[0x60];
9109 };
9110 
9111 struct mlx5_ifc_plbf_reg_bits {
9112 	u8         reserved_at_0[0x8];
9113 	u8         local_port[0x8];
9114 	u8         reserved_at_10[0xd];
9115 	u8         lbf_mode[0x3];
9116 
9117 	u8         reserved_at_20[0x20];
9118 };
9119 
9120 struct mlx5_ifc_pipg_reg_bits {
9121 	u8         reserved_at_0[0x8];
9122 	u8         local_port[0x8];
9123 	u8         reserved_at_10[0x10];
9124 
9125 	u8         dic[0x1];
9126 	u8         reserved_at_21[0x19];
9127 	u8         ipg[0x4];
9128 	u8         reserved_at_3e[0x2];
9129 };
9130 
9131 struct mlx5_ifc_pifr_reg_bits {
9132 	u8         reserved_at_0[0x8];
9133 	u8         local_port[0x8];
9134 	u8         reserved_at_10[0x10];
9135 
9136 	u8         reserved_at_20[0xe0];
9137 
9138 	u8         port_filter[8][0x20];
9139 
9140 	u8         port_filter_update_en[8][0x20];
9141 };
9142 
9143 struct mlx5_ifc_pfcc_reg_bits {
9144 	u8         reserved_at_0[0x8];
9145 	u8         local_port[0x8];
9146 	u8         reserved_at_10[0xb];
9147 	u8         ppan_mask_n[0x1];
9148 	u8         minor_stall_mask[0x1];
9149 	u8         critical_stall_mask[0x1];
9150 	u8         reserved_at_1e[0x2];
9151 
9152 	u8         ppan[0x4];
9153 	u8         reserved_at_24[0x4];
9154 	u8         prio_mask_tx[0x8];
9155 	u8         reserved_at_30[0x8];
9156 	u8         prio_mask_rx[0x8];
9157 
9158 	u8         pptx[0x1];
9159 	u8         aptx[0x1];
9160 	u8         pptx_mask_n[0x1];
9161 	u8         reserved_at_43[0x5];
9162 	u8         pfctx[0x8];
9163 	u8         reserved_at_50[0x10];
9164 
9165 	u8         pprx[0x1];
9166 	u8         aprx[0x1];
9167 	u8         pprx_mask_n[0x1];
9168 	u8         reserved_at_63[0x5];
9169 	u8         pfcrx[0x8];
9170 	u8         reserved_at_70[0x10];
9171 
9172 	u8         device_stall_minor_watermark[0x10];
9173 	u8         device_stall_critical_watermark[0x10];
9174 
9175 	u8         reserved_at_a0[0x60];
9176 };
9177 
9178 struct mlx5_ifc_pelc_reg_bits {
9179 	u8         op[0x4];
9180 	u8         reserved_at_4[0x4];
9181 	u8         local_port[0x8];
9182 	u8         reserved_at_10[0x10];
9183 
9184 	u8         op_admin[0x8];
9185 	u8         op_capability[0x8];
9186 	u8         op_request[0x8];
9187 	u8         op_active[0x8];
9188 
9189 	u8         admin[0x40];
9190 
9191 	u8         capability[0x40];
9192 
9193 	u8         request[0x40];
9194 
9195 	u8         active[0x40];
9196 
9197 	u8         reserved_at_140[0x80];
9198 };
9199 
9200 struct mlx5_ifc_peir_reg_bits {
9201 	u8         reserved_at_0[0x8];
9202 	u8         local_port[0x8];
9203 	u8         reserved_at_10[0x10];
9204 
9205 	u8         reserved_at_20[0xc];
9206 	u8         error_count[0x4];
9207 	u8         reserved_at_30[0x10];
9208 
9209 	u8         reserved_at_40[0xc];
9210 	u8         lane[0x4];
9211 	u8         reserved_at_50[0x8];
9212 	u8         error_type[0x8];
9213 };
9214 
9215 struct mlx5_ifc_mpegc_reg_bits {
9216 	u8         reserved_at_0[0x30];
9217 	u8         field_select[0x10];
9218 
9219 	u8         tx_overflow_sense[0x1];
9220 	u8         mark_cqe[0x1];
9221 	u8         mark_cnp[0x1];
9222 	u8         reserved_at_43[0x1b];
9223 	u8         tx_lossy_overflow_oper[0x2];
9224 
9225 	u8         reserved_at_60[0x100];
9226 };
9227 
9228 enum {
9229 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9230 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9231 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9232 };
9233 
9234 struct mlx5_ifc_mtutc_reg_bits {
9235 	u8         reserved_at_0[0x1c];
9236 	u8         operation[0x4];
9237 
9238 	u8         freq_adjustment[0x20];
9239 
9240 	u8         reserved_at_40[0x40];
9241 
9242 	u8         utc_sec[0x20];
9243 
9244 	u8         reserved_at_a0[0x2];
9245 	u8         utc_nsec[0x1e];
9246 
9247 	u8         time_adjustment[0x20];
9248 };
9249 
9250 struct mlx5_ifc_pcam_enhanced_features_bits {
9251 	u8         reserved_at_0[0x68];
9252 	u8         fec_50G_per_lane_in_pplm[0x1];
9253 	u8         reserved_at_69[0x4];
9254 	u8         rx_icrc_encapsulated_counter[0x1];
9255 	u8	   reserved_at_6e[0x4];
9256 	u8         ptys_extended_ethernet[0x1];
9257 	u8	   reserved_at_73[0x3];
9258 	u8         pfcc_mask[0x1];
9259 	u8         reserved_at_77[0x3];
9260 	u8         per_lane_error_counters[0x1];
9261 	u8         rx_buffer_fullness_counters[0x1];
9262 	u8         ptys_connector_type[0x1];
9263 	u8         reserved_at_7d[0x1];
9264 	u8         ppcnt_discard_group[0x1];
9265 	u8         ppcnt_statistical_group[0x1];
9266 };
9267 
9268 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9269 	u8         port_access_reg_cap_mask_127_to_96[0x20];
9270 	u8         port_access_reg_cap_mask_95_to_64[0x20];
9271 
9272 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
9273 	u8         pplm[0x1];
9274 	u8         port_access_reg_cap_mask_34_to_32[0x3];
9275 
9276 	u8         port_access_reg_cap_mask_31_to_13[0x13];
9277 	u8         pbmc[0x1];
9278 	u8         pptb[0x1];
9279 	u8         port_access_reg_cap_mask_10_to_09[0x2];
9280 	u8         ppcnt[0x1];
9281 	u8         port_access_reg_cap_mask_07_to_00[0x8];
9282 };
9283 
9284 struct mlx5_ifc_pcam_reg_bits {
9285 	u8         reserved_at_0[0x8];
9286 	u8         feature_group[0x8];
9287 	u8         reserved_at_10[0x8];
9288 	u8         access_reg_group[0x8];
9289 
9290 	u8         reserved_at_20[0x20];
9291 
9292 	union {
9293 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9294 		u8         reserved_at_0[0x80];
9295 	} port_access_reg_cap_mask;
9296 
9297 	u8         reserved_at_c0[0x80];
9298 
9299 	union {
9300 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9301 		u8         reserved_at_0[0x80];
9302 	} feature_cap_mask;
9303 
9304 	u8         reserved_at_1c0[0xc0];
9305 };
9306 
9307 struct mlx5_ifc_mcam_enhanced_features_bits {
9308 	u8         reserved_at_0[0x6b];
9309 	u8         ptpcyc2realtime_modify[0x1];
9310 	u8         reserved_at_6c[0x2];
9311 	u8         pci_status_and_power[0x1];
9312 	u8         reserved_at_6f[0x5];
9313 	u8         mark_tx_action_cnp[0x1];
9314 	u8         mark_tx_action_cqe[0x1];
9315 	u8         dynamic_tx_overflow[0x1];
9316 	u8         reserved_at_77[0x4];
9317 	u8         pcie_outbound_stalled[0x1];
9318 	u8         tx_overflow_buffer_pkt[0x1];
9319 	u8         mtpps_enh_out_per_adj[0x1];
9320 	u8         mtpps_fs[0x1];
9321 	u8         pcie_performance_group[0x1];
9322 };
9323 
9324 struct mlx5_ifc_mcam_access_reg_bits {
9325 	u8         reserved_at_0[0x1c];
9326 	u8         mcda[0x1];
9327 	u8         mcc[0x1];
9328 	u8         mcqi[0x1];
9329 	u8         mcqs[0x1];
9330 
9331 	u8         regs_95_to_87[0x9];
9332 	u8         mpegc[0x1];
9333 	u8         mtutc[0x1];
9334 	u8         regs_84_to_68[0x11];
9335 	u8         tracer_registers[0x4];
9336 
9337 	u8         regs_63_to_32[0x20];
9338 	u8         regs_31_to_0[0x20];
9339 };
9340 
9341 struct mlx5_ifc_mcam_access_reg_bits1 {
9342 	u8         regs_127_to_96[0x20];
9343 
9344 	u8         regs_95_to_64[0x20];
9345 
9346 	u8         regs_63_to_32[0x20];
9347 
9348 	u8         regs_31_to_0[0x20];
9349 };
9350 
9351 struct mlx5_ifc_mcam_access_reg_bits2 {
9352 	u8         regs_127_to_99[0x1d];
9353 	u8         mirc[0x1];
9354 	u8         regs_97_to_96[0x2];
9355 
9356 	u8         regs_95_to_64[0x20];
9357 
9358 	u8         regs_63_to_32[0x20];
9359 
9360 	u8         regs_31_to_0[0x20];
9361 };
9362 
9363 struct mlx5_ifc_mcam_reg_bits {
9364 	u8         reserved_at_0[0x8];
9365 	u8         feature_group[0x8];
9366 	u8         reserved_at_10[0x8];
9367 	u8         access_reg_group[0x8];
9368 
9369 	u8         reserved_at_20[0x20];
9370 
9371 	union {
9372 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
9373 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9374 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9375 		u8         reserved_at_0[0x80];
9376 	} mng_access_reg_cap_mask;
9377 
9378 	u8         reserved_at_c0[0x80];
9379 
9380 	union {
9381 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9382 		u8         reserved_at_0[0x80];
9383 	} mng_feature_cap_mask;
9384 
9385 	u8         reserved_at_1c0[0x80];
9386 };
9387 
9388 struct mlx5_ifc_qcam_access_reg_cap_mask {
9389 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9390 	u8         qpdpm[0x1];
9391 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9392 	u8         qdpm[0x1];
9393 	u8         qpts[0x1];
9394 	u8         qcap[0x1];
9395 	u8         qcam_access_reg_cap_mask_0[0x1];
9396 };
9397 
9398 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9399 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9400 	u8         qpts_trust_both[0x1];
9401 };
9402 
9403 struct mlx5_ifc_qcam_reg_bits {
9404 	u8         reserved_at_0[0x8];
9405 	u8         feature_group[0x8];
9406 	u8         reserved_at_10[0x8];
9407 	u8         access_reg_group[0x8];
9408 	u8         reserved_at_20[0x20];
9409 
9410 	union {
9411 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9412 		u8  reserved_at_0[0x80];
9413 	} qos_access_reg_cap_mask;
9414 
9415 	u8         reserved_at_c0[0x80];
9416 
9417 	union {
9418 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9419 		u8  reserved_at_0[0x80];
9420 	} qos_feature_cap_mask;
9421 
9422 	u8         reserved_at_1c0[0x80];
9423 };
9424 
9425 struct mlx5_ifc_core_dump_reg_bits {
9426 	u8         reserved_at_0[0x18];
9427 	u8         core_dump_type[0x8];
9428 
9429 	u8         reserved_at_20[0x30];
9430 	u8         vhca_id[0x10];
9431 
9432 	u8         reserved_at_60[0x8];
9433 	u8         qpn[0x18];
9434 	u8         reserved_at_80[0x180];
9435 };
9436 
9437 struct mlx5_ifc_pcap_reg_bits {
9438 	u8         reserved_at_0[0x8];
9439 	u8         local_port[0x8];
9440 	u8         reserved_at_10[0x10];
9441 
9442 	u8         port_capability_mask[4][0x20];
9443 };
9444 
9445 struct mlx5_ifc_paos_reg_bits {
9446 	u8         swid[0x8];
9447 	u8         local_port[0x8];
9448 	u8         reserved_at_10[0x4];
9449 	u8         admin_status[0x4];
9450 	u8         reserved_at_18[0x4];
9451 	u8         oper_status[0x4];
9452 
9453 	u8         ase[0x1];
9454 	u8         ee[0x1];
9455 	u8         reserved_at_22[0x1c];
9456 	u8         e[0x2];
9457 
9458 	u8         reserved_at_40[0x40];
9459 };
9460 
9461 struct mlx5_ifc_pamp_reg_bits {
9462 	u8         reserved_at_0[0x8];
9463 	u8         opamp_group[0x8];
9464 	u8         reserved_at_10[0xc];
9465 	u8         opamp_group_type[0x4];
9466 
9467 	u8         start_index[0x10];
9468 	u8         reserved_at_30[0x4];
9469 	u8         num_of_indices[0xc];
9470 
9471 	u8         index_data[18][0x10];
9472 };
9473 
9474 struct mlx5_ifc_pcmr_reg_bits {
9475 	u8         reserved_at_0[0x8];
9476 	u8         local_port[0x8];
9477 	u8         reserved_at_10[0x10];
9478 
9479 	u8         entropy_force_cap[0x1];
9480 	u8         entropy_calc_cap[0x1];
9481 	u8         entropy_gre_calc_cap[0x1];
9482 	u8         reserved_at_23[0xf];
9483 	u8         rx_ts_over_crc_cap[0x1];
9484 	u8         reserved_at_33[0xb];
9485 	u8         fcs_cap[0x1];
9486 	u8         reserved_at_3f[0x1];
9487 
9488 	u8         entropy_force[0x1];
9489 	u8         entropy_calc[0x1];
9490 	u8         entropy_gre_calc[0x1];
9491 	u8         reserved_at_43[0xf];
9492 	u8         rx_ts_over_crc[0x1];
9493 	u8         reserved_at_53[0xb];
9494 	u8         fcs_chk[0x1];
9495 	u8         reserved_at_5f[0x1];
9496 };
9497 
9498 struct mlx5_ifc_lane_2_module_mapping_bits {
9499 	u8         reserved_at_0[0x6];
9500 	u8         rx_lane[0x2];
9501 	u8         reserved_at_8[0x6];
9502 	u8         tx_lane[0x2];
9503 	u8         reserved_at_10[0x8];
9504 	u8         module[0x8];
9505 };
9506 
9507 struct mlx5_ifc_bufferx_reg_bits {
9508 	u8         reserved_at_0[0x6];
9509 	u8         lossy[0x1];
9510 	u8         epsb[0x1];
9511 	u8         reserved_at_8[0xc];
9512 	u8         size[0xc];
9513 
9514 	u8         xoff_threshold[0x10];
9515 	u8         xon_threshold[0x10];
9516 };
9517 
9518 struct mlx5_ifc_set_node_in_bits {
9519 	u8         node_description[64][0x8];
9520 };
9521 
9522 struct mlx5_ifc_register_power_settings_bits {
9523 	u8         reserved_at_0[0x18];
9524 	u8         power_settings_level[0x8];
9525 
9526 	u8         reserved_at_20[0x60];
9527 };
9528 
9529 struct mlx5_ifc_register_host_endianness_bits {
9530 	u8         he[0x1];
9531 	u8         reserved_at_1[0x1f];
9532 
9533 	u8         reserved_at_20[0x60];
9534 };
9535 
9536 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9537 	u8         reserved_at_0[0x20];
9538 
9539 	u8         mkey[0x20];
9540 
9541 	u8         addressh_63_32[0x20];
9542 
9543 	u8         addressl_31_0[0x20];
9544 };
9545 
9546 struct mlx5_ifc_ud_adrs_vector_bits {
9547 	u8         dc_key[0x40];
9548 
9549 	u8         ext[0x1];
9550 	u8         reserved_at_41[0x7];
9551 	u8         destination_qp_dct[0x18];
9552 
9553 	u8         static_rate[0x4];
9554 	u8         sl_eth_prio[0x4];
9555 	u8         fl[0x1];
9556 	u8         mlid[0x7];
9557 	u8         rlid_udp_sport[0x10];
9558 
9559 	u8         reserved_at_80[0x20];
9560 
9561 	u8         rmac_47_16[0x20];
9562 
9563 	u8         rmac_15_0[0x10];
9564 	u8         tclass[0x8];
9565 	u8         hop_limit[0x8];
9566 
9567 	u8         reserved_at_e0[0x1];
9568 	u8         grh[0x1];
9569 	u8         reserved_at_e2[0x2];
9570 	u8         src_addr_index[0x8];
9571 	u8         flow_label[0x14];
9572 
9573 	u8         rgid_rip[16][0x8];
9574 };
9575 
9576 struct mlx5_ifc_pages_req_event_bits {
9577 	u8         reserved_at_0[0x10];
9578 	u8         function_id[0x10];
9579 
9580 	u8         num_pages[0x20];
9581 
9582 	u8         reserved_at_40[0xa0];
9583 };
9584 
9585 struct mlx5_ifc_eqe_bits {
9586 	u8         reserved_at_0[0x8];
9587 	u8         event_type[0x8];
9588 	u8         reserved_at_10[0x8];
9589 	u8         event_sub_type[0x8];
9590 
9591 	u8         reserved_at_20[0xe0];
9592 
9593 	union mlx5_ifc_event_auto_bits event_data;
9594 
9595 	u8         reserved_at_1e0[0x10];
9596 	u8         signature[0x8];
9597 	u8         reserved_at_1f8[0x7];
9598 	u8         owner[0x1];
9599 };
9600 
9601 enum {
9602 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9603 };
9604 
9605 struct mlx5_ifc_cmd_queue_entry_bits {
9606 	u8         type[0x8];
9607 	u8         reserved_at_8[0x18];
9608 
9609 	u8         input_length[0x20];
9610 
9611 	u8         input_mailbox_pointer_63_32[0x20];
9612 
9613 	u8         input_mailbox_pointer_31_9[0x17];
9614 	u8         reserved_at_77[0x9];
9615 
9616 	u8         command_input_inline_data[16][0x8];
9617 
9618 	u8         command_output_inline_data[16][0x8];
9619 
9620 	u8         output_mailbox_pointer_63_32[0x20];
9621 
9622 	u8         output_mailbox_pointer_31_9[0x17];
9623 	u8         reserved_at_1b7[0x9];
9624 
9625 	u8         output_length[0x20];
9626 
9627 	u8         token[0x8];
9628 	u8         signature[0x8];
9629 	u8         reserved_at_1f0[0x8];
9630 	u8         status[0x7];
9631 	u8         ownership[0x1];
9632 };
9633 
9634 struct mlx5_ifc_cmd_out_bits {
9635 	u8         status[0x8];
9636 	u8         reserved_at_8[0x18];
9637 
9638 	u8         syndrome[0x20];
9639 
9640 	u8         command_output[0x20];
9641 };
9642 
9643 struct mlx5_ifc_cmd_in_bits {
9644 	u8         opcode[0x10];
9645 	u8         reserved_at_10[0x10];
9646 
9647 	u8         reserved_at_20[0x10];
9648 	u8         op_mod[0x10];
9649 
9650 	u8         command[][0x20];
9651 };
9652 
9653 struct mlx5_ifc_cmd_if_box_bits {
9654 	u8         mailbox_data[512][0x8];
9655 
9656 	u8         reserved_at_1000[0x180];
9657 
9658 	u8         next_pointer_63_32[0x20];
9659 
9660 	u8         next_pointer_31_10[0x16];
9661 	u8         reserved_at_11b6[0xa];
9662 
9663 	u8         block_number[0x20];
9664 
9665 	u8         reserved_at_11e0[0x8];
9666 	u8         token[0x8];
9667 	u8         ctrl_signature[0x8];
9668 	u8         signature[0x8];
9669 };
9670 
9671 struct mlx5_ifc_mtt_bits {
9672 	u8         ptag_63_32[0x20];
9673 
9674 	u8         ptag_31_8[0x18];
9675 	u8         reserved_at_38[0x6];
9676 	u8         wr_en[0x1];
9677 	u8         rd_en[0x1];
9678 };
9679 
9680 struct mlx5_ifc_query_wol_rol_out_bits {
9681 	u8         status[0x8];
9682 	u8         reserved_at_8[0x18];
9683 
9684 	u8         syndrome[0x20];
9685 
9686 	u8         reserved_at_40[0x10];
9687 	u8         rol_mode[0x8];
9688 	u8         wol_mode[0x8];
9689 
9690 	u8         reserved_at_60[0x20];
9691 };
9692 
9693 struct mlx5_ifc_query_wol_rol_in_bits {
9694 	u8         opcode[0x10];
9695 	u8         reserved_at_10[0x10];
9696 
9697 	u8         reserved_at_20[0x10];
9698 	u8         op_mod[0x10];
9699 
9700 	u8         reserved_at_40[0x40];
9701 };
9702 
9703 struct mlx5_ifc_set_wol_rol_out_bits {
9704 	u8         status[0x8];
9705 	u8         reserved_at_8[0x18];
9706 
9707 	u8         syndrome[0x20];
9708 
9709 	u8         reserved_at_40[0x40];
9710 };
9711 
9712 struct mlx5_ifc_set_wol_rol_in_bits {
9713 	u8         opcode[0x10];
9714 	u8         reserved_at_10[0x10];
9715 
9716 	u8         reserved_at_20[0x10];
9717 	u8         op_mod[0x10];
9718 
9719 	u8         rol_mode_valid[0x1];
9720 	u8         wol_mode_valid[0x1];
9721 	u8         reserved_at_42[0xe];
9722 	u8         rol_mode[0x8];
9723 	u8         wol_mode[0x8];
9724 
9725 	u8         reserved_at_60[0x20];
9726 };
9727 
9728 enum {
9729 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9730 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9731 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9732 };
9733 
9734 enum {
9735 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9736 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9737 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9738 };
9739 
9740 enum {
9741 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9742 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9743 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9744 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9745 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9746 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9747 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9748 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9749 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9750 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9751 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9752 };
9753 
9754 struct mlx5_ifc_initial_seg_bits {
9755 	u8         fw_rev_minor[0x10];
9756 	u8         fw_rev_major[0x10];
9757 
9758 	u8         cmd_interface_rev[0x10];
9759 	u8         fw_rev_subminor[0x10];
9760 
9761 	u8         reserved_at_40[0x40];
9762 
9763 	u8         cmdq_phy_addr_63_32[0x20];
9764 
9765 	u8         cmdq_phy_addr_31_12[0x14];
9766 	u8         reserved_at_b4[0x2];
9767 	u8         nic_interface[0x2];
9768 	u8         log_cmdq_size[0x4];
9769 	u8         log_cmdq_stride[0x4];
9770 
9771 	u8         command_doorbell_vector[0x20];
9772 
9773 	u8         reserved_at_e0[0xf00];
9774 
9775 	u8         initializing[0x1];
9776 	u8         reserved_at_fe1[0x4];
9777 	u8         nic_interface_supported[0x3];
9778 	u8         embedded_cpu[0x1];
9779 	u8         reserved_at_fe9[0x17];
9780 
9781 	struct mlx5_ifc_health_buffer_bits health_buffer;
9782 
9783 	u8         no_dram_nic_offset[0x20];
9784 
9785 	u8         reserved_at_1220[0x6e40];
9786 
9787 	u8         reserved_at_8060[0x1f];
9788 	u8         clear_int[0x1];
9789 
9790 	u8         health_syndrome[0x8];
9791 	u8         health_counter[0x18];
9792 
9793 	u8         reserved_at_80a0[0x17fc0];
9794 };
9795 
9796 struct mlx5_ifc_mtpps_reg_bits {
9797 	u8         reserved_at_0[0xc];
9798 	u8         cap_number_of_pps_pins[0x4];
9799 	u8         reserved_at_10[0x4];
9800 	u8         cap_max_num_of_pps_in_pins[0x4];
9801 	u8         reserved_at_18[0x4];
9802 	u8         cap_max_num_of_pps_out_pins[0x4];
9803 
9804 	u8         reserved_at_20[0x24];
9805 	u8         cap_pin_3_mode[0x4];
9806 	u8         reserved_at_48[0x4];
9807 	u8         cap_pin_2_mode[0x4];
9808 	u8         reserved_at_50[0x4];
9809 	u8         cap_pin_1_mode[0x4];
9810 	u8         reserved_at_58[0x4];
9811 	u8         cap_pin_0_mode[0x4];
9812 
9813 	u8         reserved_at_60[0x4];
9814 	u8         cap_pin_7_mode[0x4];
9815 	u8         reserved_at_68[0x4];
9816 	u8         cap_pin_6_mode[0x4];
9817 	u8         reserved_at_70[0x4];
9818 	u8         cap_pin_5_mode[0x4];
9819 	u8         reserved_at_78[0x4];
9820 	u8         cap_pin_4_mode[0x4];
9821 
9822 	u8         field_select[0x20];
9823 	u8         reserved_at_a0[0x60];
9824 
9825 	u8         enable[0x1];
9826 	u8         reserved_at_101[0xb];
9827 	u8         pattern[0x4];
9828 	u8         reserved_at_110[0x4];
9829 	u8         pin_mode[0x4];
9830 	u8         pin[0x8];
9831 
9832 	u8         reserved_at_120[0x20];
9833 
9834 	u8         time_stamp[0x40];
9835 
9836 	u8         out_pulse_duration[0x10];
9837 	u8         out_periodic_adjustment[0x10];
9838 	u8         enhanced_out_periodic_adjustment[0x20];
9839 
9840 	u8         reserved_at_1c0[0x20];
9841 };
9842 
9843 struct mlx5_ifc_mtppse_reg_bits {
9844 	u8         reserved_at_0[0x18];
9845 	u8         pin[0x8];
9846 	u8         event_arm[0x1];
9847 	u8         reserved_at_21[0x1b];
9848 	u8         event_generation_mode[0x4];
9849 	u8         reserved_at_40[0x40];
9850 };
9851 
9852 struct mlx5_ifc_mcqs_reg_bits {
9853 	u8         last_index_flag[0x1];
9854 	u8         reserved_at_1[0x7];
9855 	u8         fw_device[0x8];
9856 	u8         component_index[0x10];
9857 
9858 	u8         reserved_at_20[0x10];
9859 	u8         identifier[0x10];
9860 
9861 	u8         reserved_at_40[0x17];
9862 	u8         component_status[0x5];
9863 	u8         component_update_state[0x4];
9864 
9865 	u8         last_update_state_changer_type[0x4];
9866 	u8         last_update_state_changer_host_id[0x4];
9867 	u8         reserved_at_68[0x18];
9868 };
9869 
9870 struct mlx5_ifc_mcqi_cap_bits {
9871 	u8         supported_info_bitmask[0x20];
9872 
9873 	u8         component_size[0x20];
9874 
9875 	u8         max_component_size[0x20];
9876 
9877 	u8         log_mcda_word_size[0x4];
9878 	u8         reserved_at_64[0xc];
9879 	u8         mcda_max_write_size[0x10];
9880 
9881 	u8         rd_en[0x1];
9882 	u8         reserved_at_81[0x1];
9883 	u8         match_chip_id[0x1];
9884 	u8         match_psid[0x1];
9885 	u8         check_user_timestamp[0x1];
9886 	u8         match_base_guid_mac[0x1];
9887 	u8         reserved_at_86[0x1a];
9888 };
9889 
9890 struct mlx5_ifc_mcqi_version_bits {
9891 	u8         reserved_at_0[0x2];
9892 	u8         build_time_valid[0x1];
9893 	u8         user_defined_time_valid[0x1];
9894 	u8         reserved_at_4[0x14];
9895 	u8         version_string_length[0x8];
9896 
9897 	u8         version[0x20];
9898 
9899 	u8         build_time[0x40];
9900 
9901 	u8         user_defined_time[0x40];
9902 
9903 	u8         build_tool_version[0x20];
9904 
9905 	u8         reserved_at_e0[0x20];
9906 
9907 	u8         version_string[92][0x8];
9908 };
9909 
9910 struct mlx5_ifc_mcqi_activation_method_bits {
9911 	u8         pending_server_ac_power_cycle[0x1];
9912 	u8         pending_server_dc_power_cycle[0x1];
9913 	u8         pending_server_reboot[0x1];
9914 	u8         pending_fw_reset[0x1];
9915 	u8         auto_activate[0x1];
9916 	u8         all_hosts_sync[0x1];
9917 	u8         device_hw_reset[0x1];
9918 	u8         reserved_at_7[0x19];
9919 };
9920 
9921 union mlx5_ifc_mcqi_reg_data_bits {
9922 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9923 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9924 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9925 };
9926 
9927 struct mlx5_ifc_mcqi_reg_bits {
9928 	u8         read_pending_component[0x1];
9929 	u8         reserved_at_1[0xf];
9930 	u8         component_index[0x10];
9931 
9932 	u8         reserved_at_20[0x20];
9933 
9934 	u8         reserved_at_40[0x1b];
9935 	u8         info_type[0x5];
9936 
9937 	u8         info_size[0x20];
9938 
9939 	u8         offset[0x20];
9940 
9941 	u8         reserved_at_a0[0x10];
9942 	u8         data_size[0x10];
9943 
9944 	union mlx5_ifc_mcqi_reg_data_bits data[];
9945 };
9946 
9947 struct mlx5_ifc_mcc_reg_bits {
9948 	u8         reserved_at_0[0x4];
9949 	u8         time_elapsed_since_last_cmd[0xc];
9950 	u8         reserved_at_10[0x8];
9951 	u8         instruction[0x8];
9952 
9953 	u8         reserved_at_20[0x10];
9954 	u8         component_index[0x10];
9955 
9956 	u8         reserved_at_40[0x8];
9957 	u8         update_handle[0x18];
9958 
9959 	u8         handle_owner_type[0x4];
9960 	u8         handle_owner_host_id[0x4];
9961 	u8         reserved_at_68[0x1];
9962 	u8         control_progress[0x7];
9963 	u8         error_code[0x8];
9964 	u8         reserved_at_78[0x4];
9965 	u8         control_state[0x4];
9966 
9967 	u8         component_size[0x20];
9968 
9969 	u8         reserved_at_a0[0x60];
9970 };
9971 
9972 struct mlx5_ifc_mcda_reg_bits {
9973 	u8         reserved_at_0[0x8];
9974 	u8         update_handle[0x18];
9975 
9976 	u8         offset[0x20];
9977 
9978 	u8         reserved_at_40[0x10];
9979 	u8         size[0x10];
9980 
9981 	u8         reserved_at_60[0x20];
9982 
9983 	u8         data[][0x20];
9984 };
9985 
9986 enum {
9987 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9988 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9989 };
9990 
9991 enum {
9992 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9993 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9994 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9995 };
9996 
9997 struct mlx5_ifc_mfrl_reg_bits {
9998 	u8         reserved_at_0[0x20];
9999 
10000 	u8         reserved_at_20[0x2];
10001 	u8         pci_sync_for_fw_update_start[0x1];
10002 	u8         pci_sync_for_fw_update_resp[0x2];
10003 	u8         rst_type_sel[0x3];
10004 	u8         reserved_at_28[0x8];
10005 	u8         reset_type[0x8];
10006 	u8         reset_level[0x8];
10007 };
10008 
10009 struct mlx5_ifc_mirc_reg_bits {
10010 	u8         reserved_at_0[0x18];
10011 	u8         status_code[0x8];
10012 
10013 	u8         reserved_at_20[0x20];
10014 };
10015 
10016 struct mlx5_ifc_pddr_monitor_opcode_bits {
10017 	u8         reserved_at_0[0x10];
10018 	u8         monitor_opcode[0x10];
10019 };
10020 
10021 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10022 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10023 	u8         reserved_at_0[0x20];
10024 };
10025 
10026 enum {
10027 	/* Monitor opcodes */
10028 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10029 };
10030 
10031 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10032 	u8         reserved_at_0[0x10];
10033 	u8         group_opcode[0x10];
10034 
10035 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10036 
10037 	u8         reserved_at_40[0x20];
10038 
10039 	u8         status_message[59][0x20];
10040 };
10041 
10042 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10043 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10044 	u8         reserved_at_0[0x7c0];
10045 };
10046 
10047 enum {
10048 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10049 };
10050 
10051 struct mlx5_ifc_pddr_reg_bits {
10052 	u8         reserved_at_0[0x8];
10053 	u8         local_port[0x8];
10054 	u8         pnat[0x2];
10055 	u8         reserved_at_12[0xe];
10056 
10057 	u8         reserved_at_20[0x18];
10058 	u8         page_select[0x8];
10059 
10060 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10061 };
10062 
10063 union mlx5_ifc_ports_control_registers_document_bits {
10064 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10065 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10066 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10067 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10068 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10069 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10070 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10071 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10072 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10073 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10074 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
10075 	struct mlx5_ifc_paos_reg_bits paos_reg;
10076 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
10077 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10078 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
10079 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10080 	struct mlx5_ifc_peir_reg_bits peir_reg;
10081 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
10082 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10083 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10084 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10085 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
10086 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
10087 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
10088 	struct mlx5_ifc_plib_reg_bits plib_reg;
10089 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
10090 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10091 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10092 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10093 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10094 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10095 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10096 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10097 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
10098 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10099 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
10100 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10101 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
10102 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
10103 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10104 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10105 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
10106 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
10107 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
10108 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10109 	struct mlx5_ifc_pude_reg_bits pude_reg;
10110 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10111 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
10112 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
10113 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10114 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10115 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10116 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10117 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10118 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10119 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
10120 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
10121 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
10122 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10123 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10124 	u8         reserved_at_0[0x60e0];
10125 };
10126 
10127 union mlx5_ifc_debug_enhancements_document_bits {
10128 	struct mlx5_ifc_health_buffer_bits health_buffer;
10129 	u8         reserved_at_0[0x200];
10130 };
10131 
10132 union mlx5_ifc_uplink_pci_interface_document_bits {
10133 	struct mlx5_ifc_initial_seg_bits initial_seg;
10134 	u8         reserved_at_0[0x20060];
10135 };
10136 
10137 struct mlx5_ifc_set_flow_table_root_out_bits {
10138 	u8         status[0x8];
10139 	u8         reserved_at_8[0x18];
10140 
10141 	u8         syndrome[0x20];
10142 
10143 	u8         reserved_at_40[0x40];
10144 };
10145 
10146 struct mlx5_ifc_set_flow_table_root_in_bits {
10147 	u8         opcode[0x10];
10148 	u8         reserved_at_10[0x10];
10149 
10150 	u8         reserved_at_20[0x10];
10151 	u8         op_mod[0x10];
10152 
10153 	u8         other_vport[0x1];
10154 	u8         reserved_at_41[0xf];
10155 	u8         vport_number[0x10];
10156 
10157 	u8         reserved_at_60[0x20];
10158 
10159 	u8         table_type[0x8];
10160 	u8         reserved_at_88[0x7];
10161 	u8         table_of_other_vport[0x1];
10162 	u8         table_vport_number[0x10];
10163 
10164 	u8         reserved_at_a0[0x8];
10165 	u8         table_id[0x18];
10166 
10167 	u8         reserved_at_c0[0x8];
10168 	u8         underlay_qpn[0x18];
10169 	u8         table_eswitch_owner_vhca_id_valid[0x1];
10170 	u8         reserved_at_e1[0xf];
10171 	u8         table_eswitch_owner_vhca_id[0x10];
10172 	u8         reserved_at_100[0x100];
10173 };
10174 
10175 enum {
10176 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10177 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10178 };
10179 
10180 struct mlx5_ifc_modify_flow_table_out_bits {
10181 	u8         status[0x8];
10182 	u8         reserved_at_8[0x18];
10183 
10184 	u8         syndrome[0x20];
10185 
10186 	u8         reserved_at_40[0x40];
10187 };
10188 
10189 struct mlx5_ifc_modify_flow_table_in_bits {
10190 	u8         opcode[0x10];
10191 	u8         reserved_at_10[0x10];
10192 
10193 	u8         reserved_at_20[0x10];
10194 	u8         op_mod[0x10];
10195 
10196 	u8         other_vport[0x1];
10197 	u8         reserved_at_41[0xf];
10198 	u8         vport_number[0x10];
10199 
10200 	u8         reserved_at_60[0x10];
10201 	u8         modify_field_select[0x10];
10202 
10203 	u8         table_type[0x8];
10204 	u8         reserved_at_88[0x18];
10205 
10206 	u8         reserved_at_a0[0x8];
10207 	u8         table_id[0x18];
10208 
10209 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
10210 };
10211 
10212 struct mlx5_ifc_ets_tcn_config_reg_bits {
10213 	u8         g[0x1];
10214 	u8         b[0x1];
10215 	u8         r[0x1];
10216 	u8         reserved_at_3[0x9];
10217 	u8         group[0x4];
10218 	u8         reserved_at_10[0x9];
10219 	u8         bw_allocation[0x7];
10220 
10221 	u8         reserved_at_20[0xc];
10222 	u8         max_bw_units[0x4];
10223 	u8         reserved_at_30[0x8];
10224 	u8         max_bw_value[0x8];
10225 };
10226 
10227 struct mlx5_ifc_ets_global_config_reg_bits {
10228 	u8         reserved_at_0[0x2];
10229 	u8         r[0x1];
10230 	u8         reserved_at_3[0x1d];
10231 
10232 	u8         reserved_at_20[0xc];
10233 	u8         max_bw_units[0x4];
10234 	u8         reserved_at_30[0x8];
10235 	u8         max_bw_value[0x8];
10236 };
10237 
10238 struct mlx5_ifc_qetc_reg_bits {
10239 	u8                                         reserved_at_0[0x8];
10240 	u8                                         port_number[0x8];
10241 	u8                                         reserved_at_10[0x30];
10242 
10243 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10244 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10245 };
10246 
10247 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10248 	u8         e[0x1];
10249 	u8         reserved_at_01[0x0b];
10250 	u8         prio[0x04];
10251 };
10252 
10253 struct mlx5_ifc_qpdpm_reg_bits {
10254 	u8                                     reserved_at_0[0x8];
10255 	u8                                     local_port[0x8];
10256 	u8                                     reserved_at_10[0x10];
10257 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10258 };
10259 
10260 struct mlx5_ifc_qpts_reg_bits {
10261 	u8         reserved_at_0[0x8];
10262 	u8         local_port[0x8];
10263 	u8         reserved_at_10[0x2d];
10264 	u8         trust_state[0x3];
10265 };
10266 
10267 struct mlx5_ifc_pptb_reg_bits {
10268 	u8         reserved_at_0[0x2];
10269 	u8         mm[0x2];
10270 	u8         reserved_at_4[0x4];
10271 	u8         local_port[0x8];
10272 	u8         reserved_at_10[0x6];
10273 	u8         cm[0x1];
10274 	u8         um[0x1];
10275 	u8         pm[0x8];
10276 
10277 	u8         prio_x_buff[0x20];
10278 
10279 	u8         pm_msb[0x8];
10280 	u8         reserved_at_48[0x10];
10281 	u8         ctrl_buff[0x4];
10282 	u8         untagged_buff[0x4];
10283 };
10284 
10285 struct mlx5_ifc_sbcam_reg_bits {
10286 	u8         reserved_at_0[0x8];
10287 	u8         feature_group[0x8];
10288 	u8         reserved_at_10[0x8];
10289 	u8         access_reg_group[0x8];
10290 
10291 	u8         reserved_at_20[0x20];
10292 
10293 	u8         sb_access_reg_cap_mask[4][0x20];
10294 
10295 	u8         reserved_at_c0[0x80];
10296 
10297 	u8         sb_feature_cap_mask[4][0x20];
10298 
10299 	u8         reserved_at_1c0[0x40];
10300 
10301 	u8         cap_total_buffer_size[0x20];
10302 
10303 	u8         cap_cell_size[0x10];
10304 	u8         cap_max_pg_buffers[0x8];
10305 	u8         cap_num_pool_supported[0x8];
10306 
10307 	u8         reserved_at_240[0x8];
10308 	u8         cap_sbsr_stat_size[0x8];
10309 	u8         cap_max_tclass_data[0x8];
10310 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
10311 };
10312 
10313 struct mlx5_ifc_pbmc_reg_bits {
10314 	u8         reserved_at_0[0x8];
10315 	u8         local_port[0x8];
10316 	u8         reserved_at_10[0x10];
10317 
10318 	u8         xoff_timer_value[0x10];
10319 	u8         xoff_refresh[0x10];
10320 
10321 	u8         reserved_at_40[0x9];
10322 	u8         fullness_threshold[0x7];
10323 	u8         port_buffer_size[0x10];
10324 
10325 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
10326 
10327 	u8         reserved_at_2e0[0x80];
10328 };
10329 
10330 struct mlx5_ifc_qtct_reg_bits {
10331 	u8         reserved_at_0[0x8];
10332 	u8         port_number[0x8];
10333 	u8         reserved_at_10[0xd];
10334 	u8         prio[0x3];
10335 
10336 	u8         reserved_at_20[0x1d];
10337 	u8         tclass[0x3];
10338 };
10339 
10340 struct mlx5_ifc_mcia_reg_bits {
10341 	u8         l[0x1];
10342 	u8         reserved_at_1[0x7];
10343 	u8         module[0x8];
10344 	u8         reserved_at_10[0x8];
10345 	u8         status[0x8];
10346 
10347 	u8         i2c_device_address[0x8];
10348 	u8         page_number[0x8];
10349 	u8         device_address[0x10];
10350 
10351 	u8         reserved_at_40[0x10];
10352 	u8         size[0x10];
10353 
10354 	u8         reserved_at_60[0x20];
10355 
10356 	u8         dword_0[0x20];
10357 	u8         dword_1[0x20];
10358 	u8         dword_2[0x20];
10359 	u8         dword_3[0x20];
10360 	u8         dword_4[0x20];
10361 	u8         dword_5[0x20];
10362 	u8         dword_6[0x20];
10363 	u8         dword_7[0x20];
10364 	u8         dword_8[0x20];
10365 	u8         dword_9[0x20];
10366 	u8         dword_10[0x20];
10367 	u8         dword_11[0x20];
10368 };
10369 
10370 struct mlx5_ifc_dcbx_param_bits {
10371 	u8         dcbx_cee_cap[0x1];
10372 	u8         dcbx_ieee_cap[0x1];
10373 	u8         dcbx_standby_cap[0x1];
10374 	u8         reserved_at_3[0x5];
10375 	u8         port_number[0x8];
10376 	u8         reserved_at_10[0xa];
10377 	u8         max_application_table_size[6];
10378 	u8         reserved_at_20[0x15];
10379 	u8         version_oper[0x3];
10380 	u8         reserved_at_38[5];
10381 	u8         version_admin[0x3];
10382 	u8         willing_admin[0x1];
10383 	u8         reserved_at_41[0x3];
10384 	u8         pfc_cap_oper[0x4];
10385 	u8         reserved_at_48[0x4];
10386 	u8         pfc_cap_admin[0x4];
10387 	u8         reserved_at_50[0x4];
10388 	u8         num_of_tc_oper[0x4];
10389 	u8         reserved_at_58[0x4];
10390 	u8         num_of_tc_admin[0x4];
10391 	u8         remote_willing[0x1];
10392 	u8         reserved_at_61[3];
10393 	u8         remote_pfc_cap[4];
10394 	u8         reserved_at_68[0x14];
10395 	u8         remote_num_of_tc[0x4];
10396 	u8         reserved_at_80[0x18];
10397 	u8         error[0x8];
10398 	u8         reserved_at_a0[0x160];
10399 };
10400 
10401 struct mlx5_ifc_lagc_bits {
10402 	u8         fdb_selection_mode[0x1];
10403 	u8         reserved_at_1[0x1c];
10404 	u8         lag_state[0x3];
10405 
10406 	u8         reserved_at_20[0x14];
10407 	u8         tx_remap_affinity_2[0x4];
10408 	u8         reserved_at_38[0x4];
10409 	u8         tx_remap_affinity_1[0x4];
10410 };
10411 
10412 struct mlx5_ifc_create_lag_out_bits {
10413 	u8         status[0x8];
10414 	u8         reserved_at_8[0x18];
10415 
10416 	u8         syndrome[0x20];
10417 
10418 	u8         reserved_at_40[0x40];
10419 };
10420 
10421 struct mlx5_ifc_create_lag_in_bits {
10422 	u8         opcode[0x10];
10423 	u8         reserved_at_10[0x10];
10424 
10425 	u8         reserved_at_20[0x10];
10426 	u8         op_mod[0x10];
10427 
10428 	struct mlx5_ifc_lagc_bits ctx;
10429 };
10430 
10431 struct mlx5_ifc_modify_lag_out_bits {
10432 	u8         status[0x8];
10433 	u8         reserved_at_8[0x18];
10434 
10435 	u8         syndrome[0x20];
10436 
10437 	u8         reserved_at_40[0x40];
10438 };
10439 
10440 struct mlx5_ifc_modify_lag_in_bits {
10441 	u8         opcode[0x10];
10442 	u8         reserved_at_10[0x10];
10443 
10444 	u8         reserved_at_20[0x10];
10445 	u8         op_mod[0x10];
10446 
10447 	u8         reserved_at_40[0x20];
10448 	u8         field_select[0x20];
10449 
10450 	struct mlx5_ifc_lagc_bits ctx;
10451 };
10452 
10453 struct mlx5_ifc_query_lag_out_bits {
10454 	u8         status[0x8];
10455 	u8         reserved_at_8[0x18];
10456 
10457 	u8         syndrome[0x20];
10458 
10459 	struct mlx5_ifc_lagc_bits ctx;
10460 };
10461 
10462 struct mlx5_ifc_query_lag_in_bits {
10463 	u8         opcode[0x10];
10464 	u8         reserved_at_10[0x10];
10465 
10466 	u8         reserved_at_20[0x10];
10467 	u8         op_mod[0x10];
10468 
10469 	u8         reserved_at_40[0x40];
10470 };
10471 
10472 struct mlx5_ifc_destroy_lag_out_bits {
10473 	u8         status[0x8];
10474 	u8         reserved_at_8[0x18];
10475 
10476 	u8         syndrome[0x20];
10477 
10478 	u8         reserved_at_40[0x40];
10479 };
10480 
10481 struct mlx5_ifc_destroy_lag_in_bits {
10482 	u8         opcode[0x10];
10483 	u8         reserved_at_10[0x10];
10484 
10485 	u8         reserved_at_20[0x10];
10486 	u8         op_mod[0x10];
10487 
10488 	u8         reserved_at_40[0x40];
10489 };
10490 
10491 struct mlx5_ifc_create_vport_lag_out_bits {
10492 	u8         status[0x8];
10493 	u8         reserved_at_8[0x18];
10494 
10495 	u8         syndrome[0x20];
10496 
10497 	u8         reserved_at_40[0x40];
10498 };
10499 
10500 struct mlx5_ifc_create_vport_lag_in_bits {
10501 	u8         opcode[0x10];
10502 	u8         reserved_at_10[0x10];
10503 
10504 	u8         reserved_at_20[0x10];
10505 	u8         op_mod[0x10];
10506 
10507 	u8         reserved_at_40[0x40];
10508 };
10509 
10510 struct mlx5_ifc_destroy_vport_lag_out_bits {
10511 	u8         status[0x8];
10512 	u8         reserved_at_8[0x18];
10513 
10514 	u8         syndrome[0x20];
10515 
10516 	u8         reserved_at_40[0x40];
10517 };
10518 
10519 struct mlx5_ifc_destroy_vport_lag_in_bits {
10520 	u8         opcode[0x10];
10521 	u8         reserved_at_10[0x10];
10522 
10523 	u8         reserved_at_20[0x10];
10524 	u8         op_mod[0x10];
10525 
10526 	u8         reserved_at_40[0x40];
10527 };
10528 
10529 enum {
10530 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10531 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10532 };
10533 
10534 struct mlx5_ifc_modify_memic_in_bits {
10535 	u8         opcode[0x10];
10536 	u8         uid[0x10];
10537 
10538 	u8         reserved_at_20[0x10];
10539 	u8         op_mod[0x10];
10540 
10541 	u8         reserved_at_40[0x20];
10542 
10543 	u8         reserved_at_60[0x18];
10544 	u8         memic_operation_type[0x8];
10545 
10546 	u8         memic_start_addr[0x40];
10547 
10548 	u8         reserved_at_c0[0x140];
10549 };
10550 
10551 struct mlx5_ifc_modify_memic_out_bits {
10552 	u8         status[0x8];
10553 	u8         reserved_at_8[0x18];
10554 
10555 	u8         syndrome[0x20];
10556 
10557 	u8         reserved_at_40[0x40];
10558 
10559 	u8         memic_operation_addr[0x40];
10560 
10561 	u8         reserved_at_c0[0x140];
10562 };
10563 
10564 struct mlx5_ifc_alloc_memic_in_bits {
10565 	u8         opcode[0x10];
10566 	u8         reserved_at_10[0x10];
10567 
10568 	u8         reserved_at_20[0x10];
10569 	u8         op_mod[0x10];
10570 
10571 	u8         reserved_at_30[0x20];
10572 
10573 	u8	   reserved_at_40[0x18];
10574 	u8	   log_memic_addr_alignment[0x8];
10575 
10576 	u8         range_start_addr[0x40];
10577 
10578 	u8         range_size[0x20];
10579 
10580 	u8         memic_size[0x20];
10581 };
10582 
10583 struct mlx5_ifc_alloc_memic_out_bits {
10584 	u8         status[0x8];
10585 	u8         reserved_at_8[0x18];
10586 
10587 	u8         syndrome[0x20];
10588 
10589 	u8         memic_start_addr[0x40];
10590 };
10591 
10592 struct mlx5_ifc_dealloc_memic_in_bits {
10593 	u8         opcode[0x10];
10594 	u8         reserved_at_10[0x10];
10595 
10596 	u8         reserved_at_20[0x10];
10597 	u8         op_mod[0x10];
10598 
10599 	u8         reserved_at_40[0x40];
10600 
10601 	u8         memic_start_addr[0x40];
10602 
10603 	u8         memic_size[0x20];
10604 
10605 	u8         reserved_at_e0[0x20];
10606 };
10607 
10608 struct mlx5_ifc_dealloc_memic_out_bits {
10609 	u8         status[0x8];
10610 	u8         reserved_at_8[0x18];
10611 
10612 	u8         syndrome[0x20];
10613 
10614 	u8         reserved_at_40[0x40];
10615 };
10616 
10617 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10618 	u8         opcode[0x10];
10619 	u8         uid[0x10];
10620 
10621 	u8         vhca_tunnel_id[0x10];
10622 	u8         obj_type[0x10];
10623 
10624 	u8         obj_id[0x20];
10625 
10626 	u8         reserved_at_60[0x20];
10627 };
10628 
10629 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10630 	u8         status[0x8];
10631 	u8         reserved_at_8[0x18];
10632 
10633 	u8         syndrome[0x20];
10634 
10635 	u8         obj_id[0x20];
10636 
10637 	u8         reserved_at_60[0x20];
10638 };
10639 
10640 struct mlx5_ifc_umem_bits {
10641 	u8         reserved_at_0[0x80];
10642 
10643 	u8         reserved_at_80[0x1b];
10644 	u8         log_page_size[0x5];
10645 
10646 	u8         page_offset[0x20];
10647 
10648 	u8         num_of_mtt[0x40];
10649 
10650 	struct mlx5_ifc_mtt_bits  mtt[];
10651 };
10652 
10653 struct mlx5_ifc_uctx_bits {
10654 	u8         cap[0x20];
10655 
10656 	u8         reserved_at_20[0x160];
10657 };
10658 
10659 struct mlx5_ifc_sw_icm_bits {
10660 	u8         modify_field_select[0x40];
10661 
10662 	u8	   reserved_at_40[0x18];
10663 	u8         log_sw_icm_size[0x8];
10664 
10665 	u8         reserved_at_60[0x20];
10666 
10667 	u8         sw_icm_start_addr[0x40];
10668 
10669 	u8         reserved_at_c0[0x140];
10670 };
10671 
10672 struct mlx5_ifc_geneve_tlv_option_bits {
10673 	u8         modify_field_select[0x40];
10674 
10675 	u8         reserved_at_40[0x18];
10676 	u8         geneve_option_fte_index[0x8];
10677 
10678 	u8         option_class[0x10];
10679 	u8         option_type[0x8];
10680 	u8         reserved_at_78[0x3];
10681 	u8         option_data_length[0x5];
10682 
10683 	u8         reserved_at_80[0x180];
10684 };
10685 
10686 struct mlx5_ifc_create_umem_in_bits {
10687 	u8         opcode[0x10];
10688 	u8         uid[0x10];
10689 
10690 	u8         reserved_at_20[0x10];
10691 	u8         op_mod[0x10];
10692 
10693 	u8         reserved_at_40[0x40];
10694 
10695 	struct mlx5_ifc_umem_bits  umem;
10696 };
10697 
10698 struct mlx5_ifc_create_umem_out_bits {
10699 	u8         status[0x8];
10700 	u8         reserved_at_8[0x18];
10701 
10702 	u8         syndrome[0x20];
10703 
10704 	u8         reserved_at_40[0x8];
10705 	u8         umem_id[0x18];
10706 
10707 	u8         reserved_at_60[0x20];
10708 };
10709 
10710 struct mlx5_ifc_destroy_umem_in_bits {
10711 	u8        opcode[0x10];
10712 	u8        uid[0x10];
10713 
10714 	u8        reserved_at_20[0x10];
10715 	u8        op_mod[0x10];
10716 
10717 	u8        reserved_at_40[0x8];
10718 	u8        umem_id[0x18];
10719 
10720 	u8        reserved_at_60[0x20];
10721 };
10722 
10723 struct mlx5_ifc_destroy_umem_out_bits {
10724 	u8        status[0x8];
10725 	u8        reserved_at_8[0x18];
10726 
10727 	u8        syndrome[0x20];
10728 
10729 	u8        reserved_at_40[0x40];
10730 };
10731 
10732 struct mlx5_ifc_create_uctx_in_bits {
10733 	u8         opcode[0x10];
10734 	u8         reserved_at_10[0x10];
10735 
10736 	u8         reserved_at_20[0x10];
10737 	u8         op_mod[0x10];
10738 
10739 	u8         reserved_at_40[0x40];
10740 
10741 	struct mlx5_ifc_uctx_bits  uctx;
10742 };
10743 
10744 struct mlx5_ifc_create_uctx_out_bits {
10745 	u8         status[0x8];
10746 	u8         reserved_at_8[0x18];
10747 
10748 	u8         syndrome[0x20];
10749 
10750 	u8         reserved_at_40[0x10];
10751 	u8         uid[0x10];
10752 
10753 	u8         reserved_at_60[0x20];
10754 };
10755 
10756 struct mlx5_ifc_destroy_uctx_in_bits {
10757 	u8         opcode[0x10];
10758 	u8         reserved_at_10[0x10];
10759 
10760 	u8         reserved_at_20[0x10];
10761 	u8         op_mod[0x10];
10762 
10763 	u8         reserved_at_40[0x10];
10764 	u8         uid[0x10];
10765 
10766 	u8         reserved_at_60[0x20];
10767 };
10768 
10769 struct mlx5_ifc_destroy_uctx_out_bits {
10770 	u8         status[0x8];
10771 	u8         reserved_at_8[0x18];
10772 
10773 	u8         syndrome[0x20];
10774 
10775 	u8          reserved_at_40[0x40];
10776 };
10777 
10778 struct mlx5_ifc_create_sw_icm_in_bits {
10779 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10780 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
10781 };
10782 
10783 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10784 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10785 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10786 };
10787 
10788 struct mlx5_ifc_mtrc_string_db_param_bits {
10789 	u8         string_db_base_address[0x20];
10790 
10791 	u8         reserved_at_20[0x8];
10792 	u8         string_db_size[0x18];
10793 };
10794 
10795 struct mlx5_ifc_mtrc_cap_bits {
10796 	u8         trace_owner[0x1];
10797 	u8         trace_to_memory[0x1];
10798 	u8         reserved_at_2[0x4];
10799 	u8         trc_ver[0x2];
10800 	u8         reserved_at_8[0x14];
10801 	u8         num_string_db[0x4];
10802 
10803 	u8         first_string_trace[0x8];
10804 	u8         num_string_trace[0x8];
10805 	u8         reserved_at_30[0x28];
10806 
10807 	u8         log_max_trace_buffer_size[0x8];
10808 
10809 	u8         reserved_at_60[0x20];
10810 
10811 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10812 
10813 	u8         reserved_at_280[0x180];
10814 };
10815 
10816 struct mlx5_ifc_mtrc_conf_bits {
10817 	u8         reserved_at_0[0x1c];
10818 	u8         trace_mode[0x4];
10819 	u8         reserved_at_20[0x18];
10820 	u8         log_trace_buffer_size[0x8];
10821 	u8         trace_mkey[0x20];
10822 	u8         reserved_at_60[0x3a0];
10823 };
10824 
10825 struct mlx5_ifc_mtrc_stdb_bits {
10826 	u8         string_db_index[0x4];
10827 	u8         reserved_at_4[0x4];
10828 	u8         read_size[0x18];
10829 	u8         start_offset[0x20];
10830 	u8         string_db_data[];
10831 };
10832 
10833 struct mlx5_ifc_mtrc_ctrl_bits {
10834 	u8         trace_status[0x2];
10835 	u8         reserved_at_2[0x2];
10836 	u8         arm_event[0x1];
10837 	u8         reserved_at_5[0xb];
10838 	u8         modify_field_select[0x10];
10839 	u8         reserved_at_20[0x2b];
10840 	u8         current_timestamp52_32[0x15];
10841 	u8         current_timestamp31_0[0x20];
10842 	u8         reserved_at_80[0x180];
10843 };
10844 
10845 struct mlx5_ifc_host_params_context_bits {
10846 	u8         host_number[0x8];
10847 	u8         reserved_at_8[0x7];
10848 	u8         host_pf_disabled[0x1];
10849 	u8         host_num_of_vfs[0x10];
10850 
10851 	u8         host_total_vfs[0x10];
10852 	u8         host_pci_bus[0x10];
10853 
10854 	u8         reserved_at_40[0x10];
10855 	u8         host_pci_device[0x10];
10856 
10857 	u8         reserved_at_60[0x10];
10858 	u8         host_pci_function[0x10];
10859 
10860 	u8         reserved_at_80[0x180];
10861 };
10862 
10863 struct mlx5_ifc_query_esw_functions_in_bits {
10864 	u8         opcode[0x10];
10865 	u8         reserved_at_10[0x10];
10866 
10867 	u8         reserved_at_20[0x10];
10868 	u8         op_mod[0x10];
10869 
10870 	u8         reserved_at_40[0x40];
10871 };
10872 
10873 struct mlx5_ifc_query_esw_functions_out_bits {
10874 	u8         status[0x8];
10875 	u8         reserved_at_8[0x18];
10876 
10877 	u8         syndrome[0x20];
10878 
10879 	u8         reserved_at_40[0x40];
10880 
10881 	struct mlx5_ifc_host_params_context_bits host_params_context;
10882 
10883 	u8         reserved_at_280[0x180];
10884 	u8         host_sf_enable[][0x40];
10885 };
10886 
10887 struct mlx5_ifc_sf_partition_bits {
10888 	u8         reserved_at_0[0x10];
10889 	u8         log_num_sf[0x8];
10890 	u8         log_sf_bar_size[0x8];
10891 };
10892 
10893 struct mlx5_ifc_query_sf_partitions_out_bits {
10894 	u8         status[0x8];
10895 	u8         reserved_at_8[0x18];
10896 
10897 	u8         syndrome[0x20];
10898 
10899 	u8         reserved_at_40[0x18];
10900 	u8         num_sf_partitions[0x8];
10901 
10902 	u8         reserved_at_60[0x20];
10903 
10904 	struct mlx5_ifc_sf_partition_bits sf_partition[];
10905 };
10906 
10907 struct mlx5_ifc_query_sf_partitions_in_bits {
10908 	u8         opcode[0x10];
10909 	u8         reserved_at_10[0x10];
10910 
10911 	u8         reserved_at_20[0x10];
10912 	u8         op_mod[0x10];
10913 
10914 	u8         reserved_at_40[0x40];
10915 };
10916 
10917 struct mlx5_ifc_dealloc_sf_out_bits {
10918 	u8         status[0x8];
10919 	u8         reserved_at_8[0x18];
10920 
10921 	u8         syndrome[0x20];
10922 
10923 	u8         reserved_at_40[0x40];
10924 };
10925 
10926 struct mlx5_ifc_dealloc_sf_in_bits {
10927 	u8         opcode[0x10];
10928 	u8         reserved_at_10[0x10];
10929 
10930 	u8         reserved_at_20[0x10];
10931 	u8         op_mod[0x10];
10932 
10933 	u8         reserved_at_40[0x10];
10934 	u8         function_id[0x10];
10935 
10936 	u8         reserved_at_60[0x20];
10937 };
10938 
10939 struct mlx5_ifc_alloc_sf_out_bits {
10940 	u8         status[0x8];
10941 	u8         reserved_at_8[0x18];
10942 
10943 	u8         syndrome[0x20];
10944 
10945 	u8         reserved_at_40[0x40];
10946 };
10947 
10948 struct mlx5_ifc_alloc_sf_in_bits {
10949 	u8         opcode[0x10];
10950 	u8         reserved_at_10[0x10];
10951 
10952 	u8         reserved_at_20[0x10];
10953 	u8         op_mod[0x10];
10954 
10955 	u8         reserved_at_40[0x10];
10956 	u8         function_id[0x10];
10957 
10958 	u8         reserved_at_60[0x20];
10959 };
10960 
10961 struct mlx5_ifc_affiliated_event_header_bits {
10962 	u8         reserved_at_0[0x10];
10963 	u8         obj_type[0x10];
10964 
10965 	u8         obj_id[0x20];
10966 };
10967 
10968 enum {
10969 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
10970 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
10971 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
10972 };
10973 
10974 enum {
10975 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10976 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10977 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
10978 };
10979 
10980 enum {
10981 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10982 	MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10983 	MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10984 };
10985 
10986 struct mlx5_ifc_ipsec_obj_bits {
10987 	u8         modify_field_select[0x40];
10988 	u8         full_offload[0x1];
10989 	u8         reserved_at_41[0x1];
10990 	u8         esn_en[0x1];
10991 	u8         esn_overlap[0x1];
10992 	u8         reserved_at_44[0x2];
10993 	u8         icv_length[0x2];
10994 	u8         reserved_at_48[0x4];
10995 	u8         aso_return_reg[0x4];
10996 	u8         reserved_at_50[0x10];
10997 
10998 	u8         esn_msb[0x20];
10999 
11000 	u8         reserved_at_80[0x8];
11001 	u8         dekn[0x18];
11002 
11003 	u8         salt[0x20];
11004 
11005 	u8         implicit_iv[0x40];
11006 
11007 	u8         reserved_at_100[0x700];
11008 };
11009 
11010 struct mlx5_ifc_create_ipsec_obj_in_bits {
11011 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11012 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11013 };
11014 
11015 enum {
11016 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11017 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11018 };
11019 
11020 struct mlx5_ifc_query_ipsec_obj_out_bits {
11021 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11022 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11023 };
11024 
11025 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11026 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11027 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11028 };
11029 
11030 struct mlx5_ifc_encryption_key_obj_bits {
11031 	u8         modify_field_select[0x40];
11032 
11033 	u8         reserved_at_40[0x14];
11034 	u8         key_size[0x4];
11035 	u8         reserved_at_58[0x4];
11036 	u8         key_type[0x4];
11037 
11038 	u8         reserved_at_60[0x8];
11039 	u8         pd[0x18];
11040 
11041 	u8         reserved_at_80[0x180];
11042 	u8         key[8][0x20];
11043 
11044 	u8         reserved_at_300[0x500];
11045 };
11046 
11047 struct mlx5_ifc_create_encryption_key_in_bits {
11048 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11049 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11050 };
11051 
11052 struct mlx5_ifc_sampler_obj_bits {
11053 	u8         modify_field_select[0x40];
11054 
11055 	u8         table_type[0x8];
11056 	u8         level[0x8];
11057 	u8         reserved_at_50[0xf];
11058 	u8         ignore_flow_level[0x1];
11059 
11060 	u8         sample_ratio[0x20];
11061 
11062 	u8         reserved_at_80[0x8];
11063 	u8         sample_table_id[0x18];
11064 
11065 	u8         reserved_at_a0[0x8];
11066 	u8         default_table_id[0x18];
11067 
11068 	u8         sw_steering_icm_address_rx[0x40];
11069 	u8         sw_steering_icm_address_tx[0x40];
11070 
11071 	u8         reserved_at_140[0xa0];
11072 };
11073 
11074 struct mlx5_ifc_create_sampler_obj_in_bits {
11075 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11076 	struct mlx5_ifc_sampler_obj_bits sampler_object;
11077 };
11078 
11079 struct mlx5_ifc_query_sampler_obj_out_bits {
11080 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11081 	struct mlx5_ifc_sampler_obj_bits sampler_object;
11082 };
11083 
11084 enum {
11085 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11086 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11087 };
11088 
11089 enum {
11090 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11091 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11092 };
11093 
11094 struct mlx5_ifc_tls_static_params_bits {
11095 	u8         const_2[0x2];
11096 	u8         tls_version[0x4];
11097 	u8         const_1[0x2];
11098 	u8         reserved_at_8[0x14];
11099 	u8         encryption_standard[0x4];
11100 
11101 	u8         reserved_at_20[0x20];
11102 
11103 	u8         initial_record_number[0x40];
11104 
11105 	u8         resync_tcp_sn[0x20];
11106 
11107 	u8         gcm_iv[0x20];
11108 
11109 	u8         implicit_iv[0x40];
11110 
11111 	u8         reserved_at_100[0x8];
11112 	u8         dek_index[0x18];
11113 
11114 	u8         reserved_at_120[0xe0];
11115 };
11116 
11117 struct mlx5_ifc_tls_progress_params_bits {
11118 	u8         next_record_tcp_sn[0x20];
11119 
11120 	u8         hw_resync_tcp_sn[0x20];
11121 
11122 	u8         record_tracker_state[0x2];
11123 	u8         auth_state[0x2];
11124 	u8         reserved_at_44[0x4];
11125 	u8         hw_offset_record_number[0x18];
11126 };
11127 
11128 enum {
11129 	MLX5_MTT_PERM_READ	= 1 << 0,
11130 	MLX5_MTT_PERM_WRITE	= 1 << 1,
11131 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11132 };
11133 
11134 #endif /* MLX5_IFC_H */
11135