Searched refs:max_cu_per_sh (Results 1 – 21 of 21) sorted by relevance
644 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()662 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
1538 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v6_0_get_cu_enabled()1588 adev->gfx.config.max_cu_per_sh = 8; in gfx_v6_0_constants_init()1605 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()1622 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()1639 adev->gfx.config.max_cu_per_sh = 6; in gfx_v6_0_constants_init()1656 adev->gfx.config.max_cu_per_sh = 5; in gfx_v6_0_constants_init()3601 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v6_0_get_cu_info()3620 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v6_0_get_cu_info()
150 unsigned max_cu_per_sh; member
433 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
3845 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v7_0_get_cu_active_bitmap()4285 adev->gfx.config.max_cu_per_sh = 7; in gfx_v7_0_gpu_early_init()4302 adev->gfx.config.max_cu_per_sh = 11; in gfx_v7_0_gpu_early_init()4319 adev->gfx.config.max_cu_per_sh = 8; in gfx_v7_0_gpu_early_init()4338 adev->gfx.config.max_cu_per_sh = 2; in gfx_v7_0_gpu_early_init()5172 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v7_0_get_cu_info()5191 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v7_0_get_cu_info()
1705 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()1722 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()1769 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()1788 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()1805 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()1820 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()7128 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v8_0_get_cu_active_bitmap()7146 ao_cu_num = adev->gfx.config.max_cu_per_sh; in gfx_v8_0_get_cu_info()7163 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()
467 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; in amdgpu_amdkfd_get_cu_info()
727 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; in amdgpu_atombios_get_gfx_info()
1884 cu_idx < adev->gfx.config.max_cu_per_sh; in gfx_v9_4_2_query_sq_timeout_status()1917 cu_idx < adev->gfx.config.max_cu_per_sh; in gfx_v9_4_2_reset_sq_timeout_status()
1810 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_init_always_on_cu_mask()4569 adev->gfx.config.max_cu_per_sh * in gfx_v9_0_do_edc_gpr_workarounds()7124 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); in gfx_v9_0_get_cu_active_bitmap()7175 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v9_0_get_cu_info()7177 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v9_0_get_cu_info()
673 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
858 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; in amdgpu_info_ioctl()
2010 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); in amdgpu_device_parse_gpu_info_fw()3692 adev->gfx.config.max_cu_per_sh, in amdgpu_device_init()
5183 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; in gfx_v10_0_tcp_harvest()9566 unsigned total_cu = adev->gfx.config.max_cu_per_sh * in gfx_v10_0_set_gds_init()9593 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v10_0_get_wgp_active_bitmap_per_sh()9658 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v10_0_get_cu_info()9660 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v10_0_get_cu_info()
427 *value = rdev->config.cik.max_cu_per_sh; in radeon_info_ioctl()429 *value = rdev->config.si.max_cu_per_sh; in radeon_info_ioctl()
3101 rdev->config.si.max_cu_per_sh = 8; in si_gpu_init()3118 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()3136 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()3153 rdev->config.si.max_cu_per_sh = 6; in si_gpu_init()3170 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()3293 rdev->config.si.max_cu_per_sh); in si_gpu_init()5309 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) { in si_get_cu_active_bitmap()5328 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { in si_init_ao_cu_mask()
3180 rdev->config.cik.max_cu_per_sh = 7; in cik_gpu_init()3197 rdev->config.cik.max_cu_per_sh = 11; in cik_gpu_init()3214 rdev->config.cik.max_cu_per_sh = 8; in cik_gpu_init()3233 rdev->config.cik.max_cu_per_sh = 2; in cik_gpu_init()6539 for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) { in cik_get_cu_active_bitmap()6558 for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) { in cik_init_ao_cu_mask()
2162 unsigned max_cu_per_sh; member2193 unsigned max_cu_per_sh; member
1557 uint8_t max_cu_per_sh; member1577 uint8_t max_cu_per_sh; member1602 uint8_t max_cu_per_sh; member1637 uint8_t max_cu_per_sh; member
5654 UCHAR max_cu_per_sh; member5667 UCHAR max_cu_per_sh; member
2015 uint32_t total_cu = adev->gfx.config.max_cu_per_sh * in vangogh_post_smu_init()
