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Searched refs:lower_32_bits (Results 1 – 25 of 558) sorted by relevance

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/Linux-v5.15/drivers/gpu/drm/amd/amdkfd/
Dkfd_packet_manager_v9.c54 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_v9()
61 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
65 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_v9()
69 lower_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
99 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_aldebaran()
100 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_aldebaran()
104 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_aldebaran()
108 lower_32_bits(vm_page_table_base_addr); in pm_map_process_aldebaran()
147 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_v9()
172 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_v9()
[all …]
Dkfd_packet_manager_vi.c68 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_vi()
107 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_vi()
132 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_vi()
135 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
185 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
191 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
283 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_vi()
285 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_vi()
Dkfd_mqd_manager_vi.c115 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
129 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
131 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
141 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
183 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
186 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
188 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
214 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
363 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
365 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_v10.c111 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
127 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
176 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
179 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
181 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
202 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
340 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
342 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
Dkfd_mqd_manager_v9.c158 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
179 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
225 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
228 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
230 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
253 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
395 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
397 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
/Linux-v5.15/drivers/firmware/smccc/
Dkvm_guest.c32 val[0] = lower_32_bits(res.a0); in kvm_init_hyp_services()
33 val[1] = lower_32_bits(res.a1); in kvm_init_hyp_services()
34 val[2] = lower_32_bits(res.a2); in kvm_init_hyp_services()
35 val[3] = lower_32_bits(res.a3); in kvm_init_hyp_services()
/Linux-v5.15/drivers/pci/controller/mobiveil/
Dpcie-mobiveil.c151 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ib_windows()
157 mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr), in program_ib_windows()
162 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ib_windows()
192 (lower_32_bits(size64) & WIN_SIZE_MASK); in program_ob_windows()
203 lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK), in program_ob_windows()
208 mobiveil_csr_writel(pcie, lower_32_bits(pci_addr), in program_ob_windows()
/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c342 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
354 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
362 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
370 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr)); in vcn_v2_0_mc_resume()
408 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
429 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
449 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
461 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
905 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
916 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
[all …]
Dsi_dma.c60 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); in si_dma_ring_set_wptr()
72 while ((lower_32_bits(ring->wptr) & 7) != 5) in si_dma_ring_emit_ib()
159 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start()
178 WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in si_dma_start()
225 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
278 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
325 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
326 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
349 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
352 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
[all …]
Dvcn_v3_0.c477 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
488 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
496 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
504 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); in vcn_v3_0_mc_resume()
540 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
561 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
581 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
593 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1083 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1094 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode()
[all …]
Dsdma_v2_4.c226 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_ring_set_wptr()
260 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v2_4_ring_emit_ib()
265 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
318 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
320 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
326 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
460 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
468 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_gfx_resume()
572 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
627 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
[all …]
Dvcn_v2_5.c407 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
418 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
426 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
434 lower_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr)); in vcn_v2_5_mc_resume()
471 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
492 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
512 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
524 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
889 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
900 lower_32_bits(ring->wptr)); in vcn_v2_5_start_dpg_mode()
[all …]
Dsdma_v3_0.c392 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr()
393 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
397 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr()
399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
434 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v3_0_ring_emit_ib()
439 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
492 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
494 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
500 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
699 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
[all …]
Dsdma_v5_2.c207 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_2_ring_init_cond_exec()
293 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
296 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_2_ring_set_wptr()
306 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
310 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
355 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_2_ring_emit_ib()
360 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
363 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_2_ring_emit_ib()
441 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
443 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_2_ring_emit_fence()
[all …]
Dcik_sdma.c198 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); in cik_sdma_ring_set_wptr()
233 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7); in cik_sdma_ring_emit_ib()
286 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
288 amdgpu_ring_write(ring, lower_32_bits(seq)); in cik_sdma_ring_emit_fence()
294 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
490 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in cik_sdma_gfx_resume()
637 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
692 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
742 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cik_sdma_vm_copy_pte()
744 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cik_sdma_vm_copy_pte()
[all …]
Dvcn_v1_0.c309 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
321 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
329 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
379 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
391 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
401 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
917 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
928 lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
934 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
935 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
[all …]
Dsdma_v5_0.c320 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
406 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
409 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
419 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
423 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
468 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_0_ring_emit_ib()
473 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
476 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
556 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
558 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
[all …]
/Linux-v5.15/arch/x86/include/asm/
Dmshyperv.h65 u32 input_address_lo = lower_32_bits(input_address); in hv_do_hypercall()
67 u32 output_address_lo = lower_32_bits(output_address); in hv_do_hypercall()
100 u32 input1_lo = lower_32_bits(input1); in hv_do_fast_hypercall8()
133 u32 input1_lo = lower_32_bits(input1); in hv_do_fast_hypercall16()
135 u32 input2_lo = lower_32_bits(input2); in hv_do_fast_hypercall16()
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgm20b.c83 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
86 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
89 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
105 .code_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
109 .data_dma_base = lower_32_bits(data), in gm20b_pmu_acr_bld_write()
111 .overlay_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
/Linux-v5.15/drivers/pci/controller/
Dpci-xgene.c293 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
297 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
390 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
392 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); in xgene_pcie_setup_ob_reg()
394 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
402 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
451 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim)); in xgene_pcie_setup_pims()
454 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size)); in xgene_pcie_setup_pims()
518 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
524 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); in xgene_pcie_setup_ib_reg()
Dpcie-rcar.c91 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, in rcar_pcie_set_outbound()
110 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), in rcar_pcie_set_inbound()
112 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx)); in rcar_pcie_set_inbound()
/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgm20b.c41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
60 .code_dma_base = lower_32_bits(code), in gm20b_gr_acr_bld_write()
64 .data_dma_base = lower_32_bits(data), in gm20b_gr_acr_bld_write()
/Linux-v5.15/drivers/media/pci/pt3/
Dpt3_dma.c52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
/Linux-v5.15/include/linux/
Dgoldfish.h16 __raw_writel(lower_32_bits(addr), portl); in gf_write_ptr()
26 __raw_writel(lower_32_bits(addr), portl); in gf_write_dma_addr()
/Linux-v5.15/drivers/gpu/drm/nouveau/
Dnouveau_bo74c1.c49 0x030c, lower_32_bits(mem->vma[0].addr), in nv84_bo_move_exec()
51 0x0314, lower_32_bits(mem->vma[1].addr), in nv84_bo_move_exec()

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