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Searched refs:lane_width (Results 1 – 11 of 11) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dhwmgr_ppt.h97 uint8_t lane_width; member
Dvega20_hwmgr.c3365 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_print_clock_levels() local
3459 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
3466 (lane_width == 1) ? "x1" : in vega20_print_clock_levels()
3467 (lane_width == 2) ? "x2" : in vega20_print_clock_levels()
3468 (lane_width == 3) ? "x4" : in vega20_print_clock_levels()
3469 (lane_width == 4) ? "x8" : in vega20_print_clock_levels()
3470 (lane_width == 5) ? "x12" : in vega20_print_clock_levels()
3471 (lane_width == 6) ? "x16" : "", in vega20_print_clock_levels()
3474 (current_lane_width == lane_width) ? in vega20_print_clock_levels()
Dvega10_hwmgr.c1275 bios_pcie_table->entries[i].lane_width); in vega10_setup_default_pcie_table()
4635 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega10_print_clock_levels() local
4699 lane_width = pptable->PcieLaneCount[i]; in vega10_print_clock_levels()
4706 (lane_width == 1) ? "x1" : in vega10_print_clock_levels()
4707 (lane_width == 2) ? "x2" : in vega10_print_clock_levels()
4708 (lane_width == 3) ? "x4" : in vega10_print_clock_levels()
4709 (lane_width == 4) ? "x8" : in vega10_print_clock_levels()
4710 (lane_width == 5) ? "x12" : in vega10_print_clock_levels()
4711 (lane_width == 6) ? "x16" : "", in vega10_print_clock_levels()
4713 (current_lane_width == lane_width) ? in vega10_print_clock_levels()
Dprocess_pptables_v1_0.c519 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
557 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
Dvega10_processpptables.c816 pcie_table->entries[i].lane_width = in get_pcie_table()
Dsmu7_hwmgr.c678 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
/Linux-v5.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
Darcturus_ppt.c772 uint32_t gen_speed, lane_width; in arcturus_print_clk_levels() local
928 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in arcturus_print_clk_levels()
934 (lane_width == 1) ? "x1" : in arcturus_print_clk_levels()
935 (lane_width == 2) ? "x2" : in arcturus_print_clk_levels()
936 (lane_width == 3) ? "x4" : in arcturus_print_clk_levels()
937 (lane_width == 4) ? "x8" : in arcturus_print_clk_levels()
938 (lane_width == 5) ? "x12" : in arcturus_print_clk_levels()
939 (lane_width == 6) ? "x16" : "", in arcturus_print_clk_levels()
Dnavi10_ppt.c1273 uint32_t gen_speed, lane_width; in navi10_print_clk_levels() local
1334 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in navi10_print_clk_levels()
1349 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in navi10_print_clk_levels()
Dsienna_cichlid_ppt.c1057 uint32_t gen_speed, lane_width; in sienna_cichlid_print_clk_levels() local
1123 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); in sienna_cichlid_print_clk_levels()
1139 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? in sienna_cichlid_print_clk_levels()
/Linux-v5.15/drivers/gpu/drm/radeon/
Dsi_dpm.c4681 u32 lane_width; in si_init_smc_table() local
4752 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4753 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
5898 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
5906 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5907 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
/Linux-v5.15/drivers/gpu/drm/amd/pm/powerplay/
Dsi_dpm.c5143 u32 lane_width; in si_init_smc_table() local
5214 lane_width = amdgpu_get_pcie_lanes(adev); in si_init_smc_table()
5215 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
6355 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
6363 lane_width = amdgpu_get_pcie_lanes(adev); in si_set_pcie_lane_width_in_smc()
6364 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()