Searched refs:interrupt_status_offsets (Results 1 – 4 of 4) sorted by relevance
93 } interrupt_status_offsets[6] = { { variable2963 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq()2969 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()2980 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()3084 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()3085 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
90 } interrupt_status_offsets[6] = { { variable3055 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq()3061 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()3072 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()3176 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()3177 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
90 } interrupt_status_offsets[] = { { variable3240 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()3245 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()3257 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()3286 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()3287 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
92 } interrupt_status_offsets[] = { { variable3363 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq()3369 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()3381 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()3411 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()
