Searched refs:input_clks (Results 1 – 2 of 2) sorted by relevance
269 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; member353 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); in cdns_sierra_phy_init()354 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); in cdns_sierra_phy_init()497 clk = sp->input_clks[pll_mux_parent_index[clk_index][i]]; in cdns_sierra_pll_mux_register()734 sp->input_clks[PHY_CLK] = clk; in cdns_sierra_phy_get_clocks()742 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()750 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()758 sp->input_clks[PLL0_REFCLK] = clk; in cdns_sierra_phy_get_clocks()766 sp->input_clks[PLL1_REFCLK] = clk; in cdns_sierra_phy_get_clocks()775 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); in cdns_sierra_phy_enable_clocks()[all …]
289 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; member667 clk = wiz->input_clks[mux_sel->parents[i]]; in wiz_mux_clk_register()928 wiz->input_clks[WIZ_CORE_REFCLK] = clk; in wiz_clock_init()942 wiz->input_clks[WIZ_EXT_REFCLK] = clk; in wiz_clock_init()
