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/Linux-v5.15/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,infracfg.txt1 Mediatek infracfg controller
4 The Mediatek infracfg controller provides various clocks and reset
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6765-infracfg", "syscon"
14 - "mediatek,mt6797-infracfg", "syscon"
15 - "mediatek,mt7622-infracfg", "syscon"
16 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
17 - "mediatek,mt7629-infracfg", "syscon"
18 - "mediatek,mt8135-infracfg", "syscon"
[all …]
/Linux-v5.15/drivers/soc/mediatek/
Dmtk-infracfg.c27 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
34 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
37 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
39 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
58 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
65 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
67 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
69 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection()
Dmtk-pm-domains.c43 struct regmap *infracfg; member
146 ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); in scpsys_bus_protect_enable()
190 return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); in scpsys_bus_protect_disable()
352 pd->infracfg = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,infracfg"); in scpsys_add_one_domain()
353 if (IS_ERR(pd->infracfg)) in scpsys_add_one_domain()
354 return ERR_CAST(pd->infracfg); in scpsys_add_one_domain()
Dmtk-scpsys.c153 struct regmap *infracfg; member
286 return mtk_infracfg_set_bus_protection(scp->infracfg, in scpsys_bus_protect_enable()
298 return mtk_infracfg_clear_bus_protection(scp->infracfg, in scpsys_bus_protect_disable()
461 scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in init_scp()
463 if (IS_ERR(scp->infracfg)) { in init_scp()
465 PTR_ERR(scp->infracfg)); in init_scp()
466 return ERR_CAST(scp->infracfg); in init_scp()
DMakefile4 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8183.dtsi376 infracfg: syscon@10001000 { label
377 compatible = "mediatek,mt8183-infracfg", "syscon";
429 <&infracfg CLK_INFRA_AUDIO>,
430 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
437 mediatek,infracfg = <&infracfg>;
467 mediatek,infracfg = <&infracfg>;
489 mediatek,infracfg = <&infracfg>;
508 mediatek,infracfg = <&infracfg>;
519 mediatek,infracfg = <&infracfg>;
548 mediatek,infracfg = <&infracfg>;
[all …]
Dmt8167.dtsi26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
55 mediatek,infracfg = <&infracfg>;
81 mediatek,infracfg = <&infracfg>;
92 mediatek,infracfg = <&infracfg>;
100 mediatek,infracfg = <&infracfg>;
Dmt8516.dtsi57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
188 infracfg: infracfg@10001000 { label
189 compatible = "mediatek,mt8516-infracfg", "syscon";
349 <&infracfg CLK_IFR_I2C0_SEL>,
368 <&infracfg CLK_IFR_I2C1_SEL>,
387 <&infracfg CLK_IFR_I2C2_SEL>,
Dmt7622.dtsi75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
89 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
205 infracfg: infracfg@10000000 { label
206 compatible = "mediatek,mt7622-infracfg",
217 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
219 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
242 infracfg = <&infracfg>;
251 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
296 clocks = <&infracfg CLK_INFRA_TRNG>;
604 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
Dmt8173.dtsi166 clocks = <&infracfg CLK_INFRA_CA53SEL>,
181 clocks = <&infracfg CLK_INFRA_CA53SEL>,
196 clocks = <&infracfg CLK_INFRA_CA72SEL>,
211 clocks = <&infracfg CLK_INFRA_CA72SEL>,
362 infracfg: power-controller@10001000 { label
363 compatible = "mediatek,mt8173-infracfg", "syscon";
490 mediatek,infracfg = <&infracfg>;
524 mediatek,infracfg = <&infracfg>;
542 clocks = <&infracfg CLK_INFRA_CLK_13M>,
551 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
[all …]
Dmt2712e.dtsi252 infracfg: syscon@10001000 { label
253 compatible = "mediatek,mt2712-infracfg", "syscon";
293 infracfg = <&infracfg>;
319 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
330 clocks = <&infracfg CLK_INFRA_M4U>;
347 clocks = <&infracfg CLK_INFRA_M4U>;
661 <&infracfg CLK_INFRA_AO_SPI0>;
/Linux-v5.15/drivers/net/wireless/mediatek/mt76/mt7615/
Dsoc.c23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init()
24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init()
26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
/Linux-v5.15/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt63 clocks = <&infracfg CLK_INFRA_CPUSEL>,
185 clocks = <&infracfg CLK_INFRA_CA53SEL>,
197 clocks = <&infracfg CLK_INFRA_CA53SEL>,
209 clocks = <&infracfg CLK_INFRA_CA72SEL>,
221 clocks = <&infracfg CLK_INFRA_CA72SEL>,
/Linux-v5.15/Documentation/devicetree/bindings/sound/
Dmtk-btcvsd-snd.txt7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
Dmtk-afe-pcm.txt25 clocks = <&infracfg INFRA_AUDIO>,
/Linux-v5.15/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt32 - infracfg: must contain a phandle to the infracfg controller
65 infracfg = <&infracfg>;
/Linux-v5.15/arch/arm/boot/dts/
Dmt7623.dtsi80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
277 infracfg = <&infracfg>;
305 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
307 clocks = <&infracfg CLK_INFRA_PMICSPI>,
[all …]
Dmt7629.dtsi81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
134 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
477 mediatek,infracfg = <&infracfg>;
Dmt8135.dtsi133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
185 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
Dmt7623n.dtsi108 clocks = <&infracfg CLK_INFRA_M4U>;
133 clocks = <&infracfg CLK_INFRA_SMI>,
135 <&infracfg CLK_INFRA_SMI>;
264 clocks = <&infracfg CLK_INFRA_CEC>;
Dmt2701.dtsi132 infracfg: syscon@10001000 { label
133 compatible = "mediatek,mt2701-infracfg", "syscon";
155 infracfg = <&infracfg>;
193 clocks = <&infracfg CLK_INFRA_SMI>,
195 <&infracfg CLK_INFRA_SMI>;
223 clocks = <&infracfg CLK_INFRA_M4U>;
435 clocks = <&infracfg CLK_INFRA_AUDIO>,
/Linux-v5.15/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt10 It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
29 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
/Linux-v5.15/include/linux/soc/mediatek/
Dinfracfg.h153 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
155 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
/Linux-v5.15/sound/soc/mediatek/mt8192/
Dmt8192-afe-clk.c660 afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node, in mt8192_init_clock()
662 if (IS_ERR(afe_priv->infracfg)) { in mt8192_init_clock()
664 __func__, PTR_ERR(afe_priv->infracfg)); in mt8192_init_clock()
665 return PTR_ERR(afe_priv->infracfg); in mt8192_init_clock()
/Linux-v5.15/Documentation/devicetree/bindings/media/
Dmtk-cir.txt25 clocks = <&infracfg CLK_INFRA_IRRX>;

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