Searched refs:fifo_state (Results 1 – 11 of 11) sorted by relevance
272 struct vmw_fifo_state *fifo_state = dev_priv->fifo; in vmw_local_fifo_reserve() local277 uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; in vmw_local_fifo_reserve()280 mutex_lock(&fifo_state->fifo_mutex); in vmw_local_fifo_reserve()288 BUG_ON(fifo_state->reserved_size != 0); in vmw_local_fifo_reserve()289 BUG_ON(fifo_state->dynamic_buffer != NULL); in vmw_local_fifo_reserve()291 fifo_state->reserved_size = bytes; in vmw_local_fifo_reserve()325 fifo_state->using_bounce_buffer = false; in vmw_local_fifo_reserve()339 fifo_state->using_bounce_buffer = true; in vmw_local_fifo_reserve()340 if (bytes < fifo_state->static_buffer_size) in vmw_local_fifo_reserve()341 return fifo_state->static_buffer; in vmw_local_fifo_reserve()[all …]
162 struct vmw_fifo_state *fifo_state = dev_priv->fifo; in vmw_fallback_wait() local179 down_read(&fifo_state->rwsem); in vmw_fallback_wait()227 up_read(&fifo_state->rwsem); in vmw_fallback_wait()
46 } fifo_state[HVS_NUM_CHANNELS]; member372 if (!old_hvs_state->fifo_state[channel].in_use) in vc4_atomic_commit_tail()375 ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[channel].pending_commit); in vc4_atomic_commit_tail()425 if (!hvs_state->fifo_state[channel].in_use) in vc4_atomic_commit_setup()428 hvs_state->fifo_state[channel].pending_commit = in vc4_atomic_commit_setup()670 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use; in vc4_hvs_channels_duplicate_state()672 if (!old_state->fifo_state[i].pending_commit) in vc4_hvs_channels_duplicate_state()675 state->fifo_state[i].pending_commit = in vc4_hvs_channels_duplicate_state()676 drm_crtc_commit_get(old_state->fifo_state[i].pending_commit); in vc4_hvs_channels_duplicate_state()689 if (!hvs_state->fifo_state[i].pending_commit) in vc4_hvs_channels_destroy_state()[all …]
237 u32 fifo_state; in hisi_i2c_read_rx_fifo() local247 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_read_rx_fifo()248 while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) && in hisi_i2c_read_rx_fifo()251 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_read_rx_fifo()259 if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) in hisi_i2c_read_rx_fifo()271 u32 cmd, fifo_state; in hisi_i2c_xfer_msg() local281 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_xfer_msg()282 while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) && in hisi_i2c_xfer_msg()305 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_xfer_msg()314 if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) || in hisi_i2c_xfer_msg()
245 port->fifo_state = DMA_FIFO_STATE_WILL_BE_FULL; in dma_get_state()247 port->fifo_state = DMA_FIFO_STATE_FULL; in dma_get_state()249 port->fifo_state = DMA_FIFO_STATE_EMPTY; in dma_get_state()
142 dma_fifo_states_t fifo_state; member
325 u_char fifo_state; in hfcpci_clear_fifo_rx() local330 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX; in hfcpci_clear_fifo_rx()333 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX; in hfcpci_clear_fifo_rx()335 if (fifo_state) in hfcpci_clear_fifo_rx()336 hc->hw.fifo_en ^= fifo_state; in hfcpci_clear_fifo_rx()344 if (fifo_state) in hfcpci_clear_fifo_rx()345 hc->hw.fifo_en |= fifo_state; in hfcpci_clear_fifo_rx()354 u_char fifo_state; in hfcpci_clear_fifo_tx() local359 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX; in hfcpci_clear_fifo_tx()362 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX; in hfcpci_clear_fifo_tx()[all …]
504 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size() local533 fifo_state->plane[PLANE_PRIMARY] = sprite0_start; in vlv_get_fifo_size()534 fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start; in vlv_get_fifo_size()535 fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start; in vlv_get_fifo_size()536 fifo_state->plane[PLANE_CURSOR] = 63; in vlv_get_fifo_size()1722 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo() local1757 fifo_state->plane[plane_id] = 0; in vlv_compute_fifo()1762 fifo_state->plane[plane_id] = fifo_size * rate / total_rate; in vlv_compute_fifo()1763 fifo_left -= fifo_state->plane[plane_id]; in vlv_compute_fifo()1766 fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra; in vlv_compute_fifo()[all …]
662 u64 tmp, fifo_state; in nicvf_reclaim_rbdr() local676 fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx); in nicvf_reclaim_rbdr()677 if (((fifo_state >> 62) & 0x03) == 0x3) in nicvf_reclaim_rbdr()
1107 if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL) in ia_css_debug_dump_dma_state()1109 else if (port->fifo_state == DMA_FIFO_STATE_FULL) in ia_css_debug_dump_dma_state()1111 else if (port->fifo_state == DMA_FIFO_STATE_EMPTY) in ia_css_debug_dump_dma_state()
866 struct vlv_fifo_state fifo_state; member
