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Searched refs:dsi_dcs_write_seq (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.15/drivers/gpu/drm/panel/
Dpanel-leadtek-ltk050h3146w.c247 #define dsi_dcs_write_seq(dsi, cmd, seq...) do { \ macro
264 dsi_dcs_write_seq(dsi, 0xdf, 0x93, 0x65, 0xf8); in ltk050h3146w_init_sequence()
265 dsi_dcs_write_seq(dsi, 0xb0, 0x01, 0x03, 0x02, 0x00, 0x64, 0x06, in ltk050h3146w_init_sequence()
267 dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0xb5); in ltk050h3146w_init_sequence()
268 dsi_dcs_write_seq(dsi, 0xb3, 0x00, 0xb5); in ltk050h3146w_init_sequence()
269 dsi_dcs_write_seq(dsi, 0xb7, 0x00, 0xbf, 0x00, 0x00, 0xbf, 0x00); in ltk050h3146w_init_sequence()
271 dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0xc4, 0x23, 0x07); in ltk050h3146w_init_sequence()
272 dsi_dcs_write_seq(dsi, 0xbb, 0x02, 0x01, 0x24, 0x00, 0x28, 0x0f, in ltk050h3146w_init_sequence()
274 dsi_dcs_write_seq(dsi, 0xbc, 0x0f, 0x04); in ltk050h3146w_init_sequence()
275 dsi_dcs_write_seq(dsi, 0xbe, 0x1e, 0xf2); in ltk050h3146w_init_sequence()
[all …]
Dpanel-sitronix-st7703.c165 #define dsi_dcs_write_seq(dsi, cmd, seq...) do { \ macro
183 dsi_dcs_write_seq(dsi, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83); in xbd599_init_sequence()
185 dsi_dcs_write_seq(dsi, ST7703_CMD_SETMIPI, in xbd599_init_sequence()
197 dsi_dcs_write_seq(dsi, ST7703_CMD_SETPOWER_EXT, in xbd599_init_sequence()
204 dsi_dcs_write_seq(dsi, ST7703_CMD_SETRGBIF, in xbd599_init_sequence()
215 dsi_dcs_write_seq(dsi, ST7703_CMD_SETSCR, in xbd599_init_sequence()
227 dsi_dcs_write_seq(dsi, ST7703_CMD_SETVDC, 0x4E); in xbd599_init_sequence()
233 dsi_dcs_write_seq(dsi, ST7703_CMD_SETPANEL, 0x0B); in xbd599_init_sequence()
236 dsi_dcs_write_seq(dsi, ST7703_CMD_SETCYC, 0x80); in xbd599_init_sequence()
239 dsi_dcs_write_seq(dsi, ST7703_CMD_SETDISP, in xbd599_init_sequence()
[all …]
Dpanel-elida-kd35t133.c54 #define dsi_dcs_write_seq(dsi, cmd, seq...) do { \ macro
71 dsi_dcs_write_seq(dsi, KD35T133_CMD_POSITIVEGAMMA, in kd35t133_init_sequence()
74 dsi_dcs_write_seq(dsi, KD35T133_CMD_NEGATIVEGAMMA, in kd35t133_init_sequence()
77 dsi_dcs_write_seq(dsi, KD35T133_CMD_POWERCONTROL1, 0x18, 0x17); in kd35t133_init_sequence()
78 dsi_dcs_write_seq(dsi, KD35T133_CMD_POWERCONTROL2, 0x41); in kd35t133_init_sequence()
79 dsi_dcs_write_seq(dsi, KD35T133_CMD_VCOMCONTROL, 0x00, 0x1a, 0x80); in kd35t133_init_sequence()
80 dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x48); in kd35t133_init_sequence()
81 dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PIXEL_FORMAT, 0x55); in kd35t133_init_sequence()
82 dsi_dcs_write_seq(dsi, KD35T133_CMD_INTERFACEMODECTRL, 0x00); in kd35t133_init_sequence()
83 dsi_dcs_write_seq(dsi, KD35T133_CMD_FRAMERATECTRL, 0xa0); in kd35t133_init_sequence()
[all …]
Dpanel-samsung-s6e88a0-ams452ef01.c31 #define dsi_dcs_write_seq(dsi, seq...) do { \ macro
57 dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands in s6e88a0_ams452ef01_on()
58 dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity in s6e88a0_ams452ef01_on()
68 dsi_dcs_write_seq(dsi, 0xca, in s6e88a0_ams452ef01_on()
80 dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); in s6e88a0_ams452ef01_on()
81 dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage in s6e88a0_ams452ef01_on()
82 dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in s6e88a0_ams452ef01_on()
83 dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update in s6e88a0_ams452ef01_on()
84 dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands in s6e88a0_ams452ef01_on()
Dpanel-samsung-sofef00.c37 #define dsi_dcs_write_seq(dsi, seq...) do { \ macro
70 dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
78 dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
79 dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
80 dsi_dcs_write_seq(dsi, 0xb0, 0x07); in sofef00_panel_on()
81 dsi_dcs_write_seq(dsi, 0xb6, 0x12); in sofef00_panel_on()
82 dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
83 dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); in sofef00_panel_on()
84 dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in sofef00_panel_on()
Dpanel-asus-z00t-tm5p5-n35596.c35 #define dsi_dcs_write_seq(dsi, seq...) do { \ macro
120 dsi_dcs_write_seq(dsi, 0x4f, 0x01); in tm5p5_nt35596_off()