Searched refs:dprefclk_khz (Results 1 – 16 of 16) sorted by relevance
136 clk_mgr->base.dprefclk_khz = 600000; in dce120_clk_mgr_construct()143 clk_mgr->base.dprefclk_khz = 625000; in dce121_clk_mgr_construct()
145 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()150 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn301_smu_set_dprefclk()
379 s->dprefclk_khz = sb.dprefclk * 1000; in vg_get_clk_states()802 clk_mgr->base.base.dprefclk_khz = 600000; in vg_clk_mgr_construct()
221 uint32_t dprefclk_khz; member277 …int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where th… member
160 return clk_mgr->base.dprefclk_khz; in dcn31_smu_set_dprefclk()165 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn31_smu_set_dprefclk()
692 clk_mgr->base.base.dprefclk_khz = 600000; in dcn31_clk_mgr_construct()
153 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rv1_vbios_smu_set_dprefclk()
334 clk_mgr->base.dprefclk_khz = 600000; in rv1_clk_mgr_construct()
153 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rn_vbios_smu_set_dprefclk()
440 s->dprefclk_khz = sb.dprefclk * 1000; in rn_get_clk_states()1000 clk_mgr->base.dprefclk_khz = 600000; in rn_clk_mgr_construct()
178 return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz); in dce12_get_dp_ref_freq_khz()932 clk_mgr_dce->dprefclk_khz = 600000; in dce120_clk_mgr_create()953 clk_mgr_dce->dprefclk_khz = 625000; in dce121_clk_mgr_create()
1017 clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, in get_pixel_clk_frequency_100hz()1101 clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000); in dcn20_program_pix_clk()1137 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; in dcn3_program_pix_clk()
540 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn20_clk_mgr_construct()575 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn20_clk_mgr_construct()
549 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn3_clk_mgr_construct()570 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000; in dcn3_clk_mgr_construct()
159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
1999 dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10; in dcn10_align_pixel_clocks()
